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| 型號： | HYB25D256400T-8 |
| 英文描述： | DDR Synchronous DRAM |
| 中文描述： | DDR同步DRAM |
| 文件頁數(shù)： | 56/76頁 |
| 文件大?。?/td> | 1218K |
| 代理商： | HYB25D256400T-8 |
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HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
Page 56 of 76
2002-05-06
IDD Specification and Conditions
(0
°
C
≤
T
A
≤
70
°
C
;
V
DDQ
= 2.5V
±
0.2V; V
DD
= 2.5V
±
0.2V)
Symbol
Parameter/Condition
DDR200
typical
DDR266A
typical
DDR333
typical
Unit
N
otes
typ.
max.
typ.
max.
typ.
max.
4)
I
DD0
Operating Current
: one bank; active / precharge; t
= t
; t
= t
; DQ, DM, and DQS inputs changing once per clock cycle; address and
control inputs changing once every two clock cycles
65
85
72
9
0
82
105
mA
1, 2
DD1
Operating Current
: one bank; active / read / precharge; Burst = 4;
Refer to the previous page for detailed test conditions.
67
100
74
110
84
125
mA
1, 2
X
CK
CK MI
N
VIL MA
X
; tCK = tCK MI
N
2.4
4.5
2.7
5.0
3.0
5.5
5,5
mA
mA
1, 2
I
DD2F
Precharge Floating Standby Current
: CS
≥
V
,
all banks idle;
CK MI
N
N
R
E
F
tCK = tCK MI
N
,address and other control inputs changing once per clock cycle, VI
N
=
VR
E
17
35
22
45
26
58
mA
1, 2
I
DD2Q
Precharge Quiet Standby Current
: CS
≥
V
,
all banks idle;
CK
E
≥
V
I
H
MI
N
; t
CK
= t
CK MI
N
,address and other control inputs stable at
≥
R
for DQ, DQS and DM.
Precharge Quiet Standby Current
: /CS
>
= VI
H
MI
N
CK
E >
= VI
H
MI
N
; tCK = tCK MI
N
,address and other control inputs stable at
>
= VI
H
MI
N
or
<
= VIL MA
X
; VI
N
= VR
E
F for DQ, DQS and DM.
tbd.
35
tbd.
45
tbd.
58
mA
1, 2
I
DD3P
≤
V
IL MA
X
CK
CK MI
N
I
N
R
E
F
for DQ, DQS and DM.
12
15
12
15
12
15
mA
1, 2
inputs changing twice per clock cycle; address and control inputs changing
once per clock cycle
25
35
32
45
38
58
mA
1, 2
I
DD4R
one bank active; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle; DQ and DQS
outputs changing twice per clock cycle; CL = 2 for DDR200, and
DDR266A, CL=3 for DDR333; t
CK
= t
CK MI
N
; I
OUT
= 0mA
54
9
0
6
9
110
83
120
mA
1, 2
W
= 0mA
65
9
5
84
110
102
130
mA
1, 2
I
DD5
Auto-Refresh Current
: t
RC
= t
RFC MI
N
,
distributed refresh
142
180
153
1
9
0
161
205
mA
1, 2
I
DD6
1.
9
2.5
1.
9
2.5
1.
2.5
mA
mA
1, 2,
3
low power version
tbd.
tbd.
tbd.
tbd.
tbd.
tbd.
mA
1, 2,
3
I
DD7
Operating Current:
four bank; four bank interleaving with BL=4;
Refer to the previous page for detailed test conditions.
IDD6
Self-Refresh Current
: CK
E <
= 0.2V; external clock on; tCK = tCK MI
N
164
270
221
280
235
350
mA
mA
1, 2
1, 2, 3
1. I
DD
specifications are tested after the device is properly initialized and measured
at 100 M
H
z for DDR200, 133 M
.
3.
E
nables on-chip refresh and address counters
4. Test condition for typical values : V
= 2.5V ,Ta = 25
DD
= 2.7V ,
2. Input slew rate = 1V/ns.
3.
E
nables on-chip refresh and address counters
4. Test condition for typical values : VDD = 2.5V ,Ta = 25°C, test condition for maximum values: test limit at VDD = 2.7V ,Ta = 10°C
4
max
max
max
IDD2P
2,4
4,5
2,7
5,0
3,0
1, 2
IDD2F
17
35
22
45
26
58
mA
1, 2
IDD2Q
12
35
16
45
1
9
58
mA
1, 2
IDD3P
12
15
12
15
12
15
mA
1, 2
IDD5
142
180
153
1
9
0
161
205
mA
1, 2
standard version
1,
9
2,5
1,
9
2,5
1,
9
0,
9
1,0
0,
9
1,0
0,
9
1,0
mA
mA
1, 2
1, 2
235
350
102
280
65
9
5
84
110
1, 2
54
9
0
6
9
110
83
1, 2
45
38
1, 2
67
100
74
110
84
1, 2
: four bank; four bank interleaving with BL=4;
65
85
72
25
35
32
164
270
221
Auto-Refresh Current
: tRC = tRFC MI
N
, distributed refresh
Active Power-Down Standby Current
: one bank active; power-down mode; CK
E <
= VIL
MA
X
Active Standby Current
E >
=
VI
H
OperatingCurrent
: one bank active; Burst = 2; reads; continuous burst; address and
control inputs changing once per clock cycle; 50
%
of data outputs changing on every
clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MI
N
; IOUT
Operating Current
: one bank active; Burst = 2; writes; continuous burst; address and
control inputs changing once per clock cycle; 50
%
of data outputs changing on every
clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MI
N
Precharge Floating Standby Current
: /CS
>
= VI
H
MI
N
, all banks idle; CK
E >
= VI
H
MI
N
;
Precharge Power-Down Standby Current
: all banks idle; power-down mode; CK
E <
=
Operating Current
: one bank; active / precharge; tRC = tRC MI
N
; tCK = tCK MI
N
; DQ,
9
0
82
105
mA
IDD0
1. IDD specifications are tested after the device is properly initialized and measured
at 100 M
H
z for DDR200, 133 M
H
z for DDR266 and 166 M
H
z for DDR333
Symbol
Unit
IDD7
Parameter/Condition
IDD4
W
IDD4R
IDD3
IDD1
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| HYB25D256800AT-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?256Mbit (32Mx8) DDR266A (2-3-3)? |
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