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參數(shù)資料
| 型號(hào)： | HYB25D256400T-8 |
| 英文描述： | DDR Synchronous DRAM |
| 中文描述： | DDR同步DRAM |
| 文件頁(yè)數(shù)： | 18/76頁(yè) |
| 文件大小： | 1218K |
| 代理商： | HYB25D256400T-8 |
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HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
Page 18 of 76
2002-05-06
Operations
Bank/Row Activation
Before any Read or
W
rite commands can be issued to a bank within the DDR SDRAM, a row in that bank
must be “opened” (activated). This is accomplished via the Active command and addresses A0-A11, BA0 and
BA1 (see Activating a Specific Row in a Specific Bank), which decode and select both the bank and the row
to be activated. After opening a row (issuing an Active command), a Read or
W
rite command may be issued
to that row, sub
j
ect to the t
RCD
specification. A subsequent Active command to a different row in the same
bank can only be issued after the previous active row has been “closed” (precharged). The minimum time
interval between successive Active commands to the same bank is defined by t
RC
. A subsequent Active com-
mand to another bank can be issued while the first bank is being accessed, which results in a reduction of
total row-access overhead. The minimum time interval between successive Active commands to different
banks is defined by t
RRD
.
Activating a Specific Row in a Specific Bank
RA
BA
H
I
GH
RA = row address.
BA = bank address.
CK
CK
CK
E
CS
RAS
CAS
WE
A0-A11
BA0, BA1
Don’t Care
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D256800AT-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?256Mbit (32Mx8) DDR266A (2-3-3)? |
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| HYB25D256800AT-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM |
| HYB25D256800BC-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-Mbit Double Data Rate SDRAM, Die Rev. B |
| HYB25D256800BC-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?256Mb (64Mx4) FBGA DDR266A (2-3-3)? |
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