參數(shù)資料
型號(hào): HYB25D128800T-7
英文描述: ?128Mb (16Mx8) DDR 266A (2-3-3)?
中文描述: ?128Mb的(16Mx8復(fù)員266A章)(2-3-3)?
文件頁(yè)數(shù): 61/76頁(yè)
文件大?。?/td> 1218K
代理商: HYB25D128800T-7
2002-05-06
Page 61 of 76
HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
Electrical Characteristics & AC Timing for DDR266 - Applicable Specifications
Expressed in Clock Cycles
(0
°
C
T
A
70
°
C
;
V
DDQ
= 2.5V
±
0.2V; V
DD
= 2.5V
±
0.2V, See AC
Characteristics)
Symbol
Parameter
DD266A
@
CL=2
Units
N
otes
Min
Max
t
MRD
Mode register set command cycle time
2
t
CK
1-5
t
W
PR
E
W
rite preamble
0.25
t
CK
1-5
t
RAS
Active to Precharge command
6
16000
t
CK
1-5
t
RC
Active to Active/Auto-refresh command period
9
t
CK
1-5
t
RFC
Auto-refresh to Active/Auto-refresh
command period
10
t
CK
1-5
t
RCD
Active to Read or
W
rite delay
3
t
CK
1-5
t
RP
Precharge command period
3
t
CK
1-5
t
RRD
Active bank A to Active bank B command
2
t
CK
1-5
t
W
R
W
rite recovery time
2
t
CK
1-5
t
DAL
Auto precharge write recovery
+
precharge time
5
t
CK
1-5
t
W
TR
Internal write to read command delay
1
t
CK
1-5
t
X
S
N
R
E
xit self-refresh to non-read command
10
t
CK
1-5
t
X
SRD
E
xit self-refresh to read command
200
t
CK
1-5
1. Input slew rate = 1V/ns
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for
signals other than CK/CK, is V
R
E
F.
3. Inputs are not recognized as valid until V
R
E
F
stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (
N
ote 3) is V
TT
.
5. t
HZ
and t
L
Z
transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a spe-
cific voltage level, but specify when the device is no longer driving (
HZ
), or begins driving (L
Z
).
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