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| 型號： | HYB25D128800T-7 |
| 英文描述： | ?128Mb (16Mx8) DDR 266A (2-3-3)? |
| 中文描述： | ？128Mb的（16Mx8復(fù)員266A章）（2-3-3）？ |
| 文件頁數(shù)： | 46/76頁 |
| 文件大?。?/td> | 1218K |
| 代理商： | HYB25D128800T-7 |
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HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
Page 46 of 76
2002-05-06
Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)
Current State
CS
H
RAS
X
CAS
X
WE
X
Command
Deselect
Action
N
otes
1-6
Any
N
OP. Continue previous operation
L
H
H
H
N
o Operation
N
OP. Continue previous operation
1-6
Idle
L
L
H
H
Active
Select and activate row
1-6
L
L
L
H
AUTO R
E
FR
E
S
H
1-7
L
L
L
L
MOD
E
R
EG
IST
E
R S
E
T
1-7
Row Active
L
H
L
H
Read
Select column and start Read burst
1-6, 10
L
H
L
L
W
rite
Select column and start
W
rite burst
1-6, 10
L
L
H
L
Precharge
Deactivate row in bank(s)
1-6, 8
Read
(Auto Precharge
Disabled)
L
H
L
H
Read
Select column and start new Read burst
1-6, 10
L
L
H
L
Precharge
Truncate Read burst, start Precharge
1-6, 8
L
H
H
L
BURST T
E
RMI
N
AT
E
BURST T
E
RMI
N
AT
E
1-6,
9
W
rite
(Auto Precharge
Disabled)
L
H
L
H
Read
Select column and start Read burst
1-6, 10, 11
L
H
L
L
W
rite
Select column and start
W
rite burst
1-6, 10
L
L
H
L
Precharge
Truncate
W
rite burst, start Precharge
1-6, 8, 11
1. This table applies when CK
E
n-1 was
H
I
GH
and CK
E
n is
H
I
GH
(see Truth Table 2: Clock
E
nable (CK
E
) and after t
X
S
N
R /
t
X
SRD
has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those
allowed to be issued to that bank when in that state.
E
xceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and t
RP
has been met.
Row Active: A row in the bank has been activated, and t
RCD
has been met.
N
o data bursts/accesses and no register accesses are
in progress.
Read:
A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
W
rite:
A
W
rite burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank.
Precharging:Starts with registration of a Precharge command and ends when t
RP
is met. Once t
RP
is met, the bank is in the idle
state.
Row Activating:Starts with registration of an Active command and ends when t
RCD
is met. Once t
RCD
is met, the bank is in the “row
active” state.
Read w/Auto Precharge
E
nabled: Starts with registration of a Read command with Auto Precharge enabled and ends when t
RP
has been met. Once t
RP
is met, the bank is in the idle state.
W
rite w/Auto Precharge
E
nabled: Starts with registration of a
W
rite command with Auto Precharge enabled and ends when t
RP
has been met. Once t
RP
is met, the bank is in the idle state.
Deselect or
N
OP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these
states. Allowable commands to the other bank are determined by its current state and according to Truth Table 4.
5. The following states must not be interrupted by any executable command; Deselect or
N
OP commands must be applied on each
positive clock edge during these states.
Refreshing: Starts with registration of an Auto Refresh command and ends when t
RFC
is met. Once t
RFC
is met, the DDR SDRAM
is in the “all banks idle” state.
Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when t
MRD
has been met. Once
t
MRD
is met, the DDR SDRAM is in the “all banks idle” state.
Precharging All: Starts with registration of a Precharge All command and ends when t
RP
is met. Once t
RP
is met, all banks is in the
idle state.
6. All states and sequences not shown are illegal or reserved.
7.
N
ot bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
9
.
N
ot bank-specific; BURST T
E
RMI
N
AT
E
affects the most recent Read burst, regardless of bank.
10. Reads or
W
rites listed in the Command/Action column include Reads or
W
rites with Auto Precharge enabled and Reads or
W
rites
with Auto Precharge disabled.
11. Requires appropriate DM masking.
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PDF描述 |
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| HYB25D128800T-7.5 | ?128Mb (16Mx8) DDR 266B (2.5-3-3)? |
| HYB25D256160BT-8 | ?256Mbit (16Mx16) DDR200 (2-2-2)? |
| HYB25D256400AT-7 | ?256Mbit (64Mx4) DDR266A (2-3-3)? |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D128800T-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?128Mb (16Mx8) DDR 266B (2.5-3-3)? |
| HYB25D128800TC-3 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:MEMORY SPECTRUM |
| HYB25D128800TC-37 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:MEMORY SPECTRUM |
| HYB25D128800TC-5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:MEMORY SPECTRUM |
| HYB25D128800TC-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:MEMORY SPECTRUM |
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