參數資料
型號： HYB18T512800AF-5
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512-Mbit Double-Data-Rate-Two SDRAM
中文描述： 512兆雙數據速率2內存
文件頁數： 81/96頁
文件大?。?/td> 1571K
代理商： HYB18T512800AF-5
2
HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Electrical Characteristics & AC Timing - Absolute Specification
Data Sheet
81
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
t
RFC
Auto-Refresh to Active/Auto-Refresh
command period
Active to Read or Write delay
(with and without Auto-Precharge)
Precharge command period
Active bank A to Active bank B command
period
105
—
105
—
ns
17)
t
RCD
15
—
15
—
ns
18)
t
RP
t
RRD
15
7.5
10
2
15
WR +
t
RP
—
—
—
15
7.5
10
2
15
WR +
t
RP
—
—
—
ns
ns
ns
t
CK
ns
t
CK
19)
20)
t
CCD
t
WR
t
DAL
CAS A to CAS B command period
Write recovery time
Auto-Precharge write recovery +
precharge time
Internal Write to Read command delay
Internal Read to Precharge command
delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit active power-down mode to Read
command (slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit Self-Refresh to Read command
Exit Self-Refresh to non-Read command
CKE minimum high and low pulse width
Average periodic refresh Interval
—
—
—
—
21)
t
WTR
t
RTP
10
7.5
—
—
7.5
7.5
—
—
ns
ns
22)
t
XARD
2
—
2
—
t
CK
23)
t
XARDS
6 - AL
—
6 - AL
—
t
CK
23)
t
XP
—
2
—
t
CK
t
XSRD
t
XSNR
t
CKE
t
REFI
200
t
RFC
+10
3
—
—
0
t
IS
+
t
CK
+
t
IH
—
—
—
—
7.8
3.9
12
200
t
RFC
+10
3
—
—
0
t
IS
+
t
CK
+
t
IH
––
—
t
CK
ns
t
CK
μ
s
μ
s
ns
ns
—
7.8
3.9
12
24)25)
26)
t
OIT
t
DELAY
OCD drive mode output delay
Minimum time clocks remain ON after CKE
asynchronously drops LOW
27)
1) V
DDQ
= 1.8V
±
0.1V;
V
DD
= 1.8V
±
0.1V) See notes
3)4)5)6)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
powered down and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1 V/ns in single ended mode. For other slew
rates see
Chapter 8
of this datasheet.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.
The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode;
The input reference level for signals other than CK/CK, DQS / DQS, RDQS / RDQS,
t
IS
,
t
iH
,
t
DS
,
t
DH
is
V
REF
.
For
t
IS
,
t
iH
,
t
DS
,
t
DH
input reference levels see
Chapter 8.3
of this datasheet.
5) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2
x
V
DDQ
is
recognized as LOW.
6) The output timing reference voltage level is
V
TT
. See
Chapter 8
for the reference load for timing measurements.
7) Min (
t
CL
,
t
CH
) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
this value can be greater than the minimum specification limits for
t
CL
and
t
CH)
.
8) For input frequency change during DRAM operation, see
Chapter 2.12
of this datasheet.
Table 40
Symbol Parameter
Timing Parameter by Speed Grade - DDR2-400 & DDR2-533
1)2)3)4)5)6)
–5
DDR2–400 3–3–3
Min.
–3.7
DDR2–533 4–4–4
Min.
Unit Notes
Max.
Max.
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