參數(shù)資料
型號(hào)： HYB18T512800AF-5
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512-Mbit Double-Data-Rate-Two SDRAM
中文描述： 512兆雙數(shù)據(jù)速率2內(nèi)存
文件頁(yè)數(shù)： 69/96頁(yè)
文件大小： 1571K
代理商： HYB18T512800AF-5
HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
AC & DC Operating Conditions
Data Sheet
69
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
5.2
DC & AC Logic Input Levels
DDR2 SDRAM pin timing are specified for either single
ended or differential mode depending on the setting of
the EMRS(1) “Enable DQS” mode bit; timing
advantages of differential mode are realized in system
design. The method by which the DDR2 SDRAM pin
timing are measured is mode dependent. In single
ended mode, timing relationships are measured
relative to the rising or falling edges of DQS crossing at
V
REF
. In differential mode, these timing relationships
are measured relative to the crosspoint of DQS and its
complement, DQS. This distinction in timing methods is
verified by design and characterization but not subject
to production test. In single ended mode, the DQS (and
RDQS) signals are internally disabled and don’t care.
Figure 63
Single-ended AC Input Test Conditions Diagram
Table 24
Symbol
V
IH(dc)
V
IL(dc)
V
IH(ac)
V
IL(ac)
Single-ended DC & AC Logic Input Levels
Parameter
DC input logic high
DC input low
AC input logic high
AC input low
Min.
V
REF
+ 0.125
–0.3
V
REF
+ 0.250
—
Max.
V
DDQ
+ 0.3
V
REF
– 0.125
—
V
REF
– 0.250
Units
V
V
V
V
Table 25
Symbol
V
REF
V
SWING(max)
SLEW
Single-ended AC Input Test Conditions
Condition
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum slew rate
Value
0.5
x
V
DDQ
1.0
1.0
Units
V
V
V / ns
Notes
1)2)
1) This timing and slew rate definition is valid for all single-ended signals except
t
IS
,
t
IH
,
t
DS
,
t
DH
.
2) Input waveform timing is referenced to the input signal crossing through the
V
REF
level applied to the device under test.
3) The input signal minimum slew rate is to be maintained over the range from
V
IL(dc)max
to
V
IH(ac)min
for rising edges and the
range from
V
IH(dc)min
to
V
IL(ac)max
for falling edges as shown in
Figure 63
4) AC timings are referenced with input waveforms switching from
V
IL(ac)
to
V
IH(ac)
on the positive transitions and
V
IH(ac)
to
V
IL(ac
on the negative transitions.
1)2)
3)4)
1.
V
DDQ
V
IH(ac)
min
V
IH(dc)
min
V
REF
V
IL(dc)
max
V
IL(ac)
max
V
SS
V
SWING(MAX)
delta TR
delta TF
Start of Falling Edge Input Timing
Start of Rising Edge Input Timing
V
IH(dc)
min - V
IL(ac)
max
delta TF
Falling Slew =
Rising Slew =V
IH(ac)
min - V
IL(dc)
max
delta TR
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