參數(shù)資料
型號： HYB18RL25632AC-3.3
英文描述： ?256M (8Mx32) 300MHz ?
中文描述： ？256M（8Mx32）300MHz的？
文件頁數(shù)： 34/36頁
文件大?。?/td> 869K
代理商： HYB18RL25632AC-3.3
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Version 1.42
Page 34
Infineon Technologies
This specification is preliminary and subject to change without notice
4
Electrical Characteristics
4.1
Absolute Maximum Ratings
Storage temperature range............................................ – 55 to + 150 C
Input/output pins voltage........................................– 0.3 to VDDQ + 0.3V
Inputs and VREF voltage.......................................– 0.3 to VDDQ + 0.3V
Power supply voltage VDD...............................................– 0.3 to + 2.1V
Power supply voltage VEXT ................................ ........... – 0.3 to + 2.8V
Power supply voltage VDDQ............................................– 0.3 to + 2.1V
Junction Temperature......................................................... 0°C to 100°C
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. This is a stress
rating only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
4.2
Recommended Power & DC Operation Ratings
All values are recommended operating conditions unless otherwise noted.
Table 13 Power & DC Operating Conditions
Note: 1. Typically the value of Vref is expected to be 0.5 * VDDQ of the transmitting device. Vref is expected to track variations in VDDQ
Note: 2. Peak to peak AC noise on Vref may not exceed 2% Vref (DC)
Note: 3. Vtt of the transmitting device must track Vref of the receiving device.
Note: 4. Recommanded on board decouping capacitors : VDDQ: 2 x 0.1μF / device, VDD: 2 x 0.1μF / device, VREF : 0.1μF / device,
VEXT: 0.1μF / device.
Parameter
Symbol
min.
2.38
1.75
1.7
0.49*
VDDQ
-5
-5
-5
-5
typ.
2.5
1.8
1.8
0.9
max.
2.63
1.85
1.9
0.51*
VDDQ
+5
+5
+5
+5
Unit
Notes
Power Supply Voltages
VEXT
VDD
VDDQ
V
V
V
V
Power Supply Voltage for I/O
Reference Voltage
Vref
1,2,3
Input leakage current
CLK Input leakage current
Output leakage current
VREF Current
II
L
II
LC
I
OL
IREF
A
A
A
A
Matched Impedance 1.8V
Input logic high voltage, DC
Input logic low voltage, DC
Output high voltage
Output low voltage
VI
H
VI
L
VOH
VOL
Vref + 0.15
VSSQ - 0.3
VDDQ
-
–
–
-
-
VDDQ + 0.3 V
Vref - 0.15
-
0
V
V
V
HSTL strong
Input logic high voltage, DC
Input logic low voltage, DC
Output high voltage
Output low voltage
VI
H
VI
L
VOH
VOL
Vref + 0.1
VSSQ - 0.3
VDDQ-0.4
-
–
–
-
-
VDDQ + 0.3 V
Vref - 0.1
-
0.4
V
V
V
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