參數(shù)資料
型號(hào)： HYB18H256321BF-14
廠商： QIMONDA AG
元件分類： DRAM
英文描述： 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM
中文描述： 8M X 32 SYNCHRONOUS GRAPHICS RAM MODULE, 0.25 ns, PBGA136
封裝： GREEN, PLASTIC, TFBGA-136
文件頁(yè)數(shù)： 7/41頁(yè)
文件大小： 1302K
代理商： HYB18H256321BF-14
HYB18H256321BF
256-Mbit GDDR3
Internet Data Sheet
Rev. 0.80, 2007-09
09132007-07EM-7OYI
7
2.2
Mirror Function
The GDDR3 Graphics RAM provides a ball mirroring feature that is enabled by applying a logic HIGH on ball MF. This function
allows for efficient routing in a clam shell configuration.
Depending of the logic state applied on MF, the command and address signals will be assigned to different balls. The default
ball configuration corresponds to MF = LOW.
The DC level (HIGH or LOW) must be applied on the MF pin at power up and is not allowed to change after that.
Table 3
shows the ball assignment as a function of the logic state applied on MF.
A<0:11>
Input
Address Inputs:
During ACTIVATE, A0-A11 defines the row address. For READ/WRITE, A2-A7 and A9 defines the
column address, and A8 defines the auto precharge bit. If A8 is HIGH, the accessed bank is
precharged after execution of the column access. If A8 is LOW, AUTO PRECHARGE is disabled and
the bank remains active. Sampled with PRECHARGE, A8 determines whether one bank is
precharged (selected by BA<0:1>, A8 LOW) or all 4 banks are precharged (A8 HIGH). During
(EXTENDED) MODE REGISTER SET the address inputs define the register settings. A<0:11> are
sampled with the positive edge of CLK.
ODT Impedance Reference:
The ZQ ball is used to control the ODT impedance.
Reset pin:
The RES pin is a
V
DDQ
CMOS input. RES is not internally terminated. When RES is at LOW state the
chip goes into full reset. The chip stays in full reset until RES goes to HIGH state. The Low to High
transition of the RES signal is used to latch the CKE value to set the value of the termination resistors
of the address and command inputs. After exiting the full reset a complete initialization is required
since the full reset sets the internal settings to default.
Mirror function pin:
The MF pin is a
V
DDQ
CMOS input. This pin must be hardwired on board either to a power or to a
ground plane. With MF set to HIGH, the command and address pins are reassigned in order to allow
for an easier routing on board for a back to back memory arrangement.
Enables Boundary Scan Functionality:
If Boundary Scan is not used PIN should be constantly connected to GND.
Voltage Reference:
V
REF
is the reference voltage input.
Power Supply:
Power and Ground for the internal logic.
I/O Power Supply:
Isolated Power and Ground for the output buffers to provide improved noise immunity.
Please do not connect No Connect and Reserved for Future Use balls.
When the MF ball is tied LOW, RFM receiver is disabled and it recommended to be driven to a static
LOW state. However, either static HIGH or floating state on this pin will not cause any problem for
the GDDR3 SGRAM. When the MF ball is tied HIGH, RAS(H3) becomes RFM due to mirror function
and the receiver is disabled. It is recommended to be driven to a static LOW state. However, either
static HIGH or floating state on this pin will not cause any problem for the GDDR3 SGRAM.
ZQ
-
RESET
Input
MF
Input
SEN
Input
V
REF
Supply
V
DD
,
V
SS
Supply
V
DDQ
,
V
SSQ
Supply
NC, RFU
RFM
-
-
Ball
Type
Detailed Function
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