參數(shù)資料
型號: HYB18H256321BF-14
廠商: QIMONDA AG
元件分類: DRAM
英文描述: 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM
中文描述: 8M X 32 SYNCHRONOUS GRAPHICS RAM MODULE, 0.25 ns, PBGA136
封裝: GREEN, PLASTIC, TFBGA-136
文件頁數(shù): 15/41頁
文件大小: 1302K
代理商: HYB18H256321BF-14
HYB18H256321BF
256-Mbit GDDR3
Internet Data Sheet
Rev. 0.80, 2007-09
09132007-07EM-7OYI
15
TABLE 7
ON/OFF mode of DQ/DM receivers
The ON/OFF state of the DQ/DM receivers depends on the Write Latency. The dependence is given in
Table 7
.
3.1.5
Test mode
The normal operating mode is selected by issuing a Mode Register Set command with bit A7 set to zero and bits A0-A6 and
A8-A11 set to the desired value.
3.1.6
DLL Reset
The normal operating mode is selected by issuing a Mode Register Set command with bit A8 set to zero and bits A0-A7 and
A9-A11 set to the desired values. A DLL Reset is initiated by issuing a Mode Register Set command with bit A8 set to one and
bits A0-A7 and A9-A11 set to the desired values. The GDDR3 Graphics RAM returns automatically in the normal mode of
operations once the DLL reset is completed.
WL
DQ/DM-Receivers
3-4
5-6-7
Receivers are always on
Receivers are off and will be switched on by Write command and will be switched off again after
WL+BL
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