參數(shù)資料
型號： HYB18H256321BF-14
廠商： QIMONDA AG
元件分類： DRAM
英文描述： 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM
中文描述： 8M X 32 SYNCHRONOUS GRAPHICS RAM MODULE, 0.25 ns, PBGA136
封裝： GREEN, PLASTIC, TFBGA-136
文件頁數(shù)： 31/41頁
文件大小： 1302K
代理商： HYB18H256321BF-14
HYB18H256321BF
256-Mbit GDDR3
Internet Data Sheet
Rev. 0.80, 2007-09
09132007-07EM-7OYI
31
4.10
Operating Current Measurement Conditions
TABLE 18
Operating Current Measurement Conditions
Symbol
Parameter/Condition
I
DD0
Operating Current - One bank, Activate - Precharge
t
CK
=min(
t
CK
),
t
RC
=min(
t
RC
)
Databus inputs are SWITCHING; Address and control inputs are SWITCHING, CS = HIGH between valid
commands.
Operating Current - One bank, Activate - Read - Precharge
One bank is accessed with
t
CK
=min(
t
CK
),
t
RC
=min(
t
RC
), CL = CL(min), Address and control inputs are SWITCHING;
CS = HIGH between valid commands. I
out
=0 mA
Precharge Power-Down Standby Current
All banks idle, power-down mode, CKE is LOW,
t
CK
=min(
t
CK
), Data bus inputs are STABLE (HIGH).
Precharge Floating Standby Current
All banks idle; CS is HIGH, CKE is HIGH,
t
CK
=min(
t
CK
); Address and control inputs are SWITCHING; Data bus input
are STABLE (HIGH).
Precharge Quiet Standby Current
CS is HIGH, all banks idle, CKE is HIGH,
t
CK
=min(
t
CK
), Address and other control inputs STABLE (HIGH), Data
bus inputs are STABLE (HIGH).
Active Power-Down Standby Current
One bank active, CKE is LOW, Address and control inputs are STABLE (HIGH); Data bus inputs are STABLE
(HIGH); standard active power-down mode.
Active Standby Current
One bank active, CS is HIGH, CKE is HIGH,
t
RAS
=
t
RAS,max
,
t
CK
=min(
t
CK
); Address and control inputs are
SWITCHING; Data bus inputs are SWITCHING.
Operating Current - Burst Read
One bank active; Continuous read bursts, CL = CL(min);
t
CK
=min(
t
CK
);
t
RAS
=
t
RAS,max
; Address and control inputs
are SWITCHING; Iout = 0 mA.
Operating Current - Burst Write
One bank active; Continuous write bursts;
t
CK
=min(
t
CK
); Address and control inputs are SWITCHING; Data bus
inputs are SWITCHING.
Burst Auto Refresh Current
Refresh command at
t
RFC
=min(t
RFC
);
t
CK
=min(
t
CK
); CKE is HIGH, CS is HIGH between all valid commands; Other
command and address inputs are SWITCHING; Data bus inputs are SWITCHING.
Distributed Auto Refresh Current
t
CK
=
t
CKmin
; Refresh command every
t
REFI
; CKE is HIGH, CS is HIGH between valid commands; Other command
and address inputs are SWITCHING; Data bus inputs are SWITCHING.
Self Refresh Current
CKE
≤
max(
V
IL
), external clock off, CK and CK LOW; Address and control inputs are STABLE (HIGH); Data Bus
inputs are STABLE (HIGH).
Operating Bank Interleave Read Current
All banks interleaving with CL = CL(min);
t
RCD
=
t
RCDRD
(min);
t
RRD
=
t
RRD
(min);
I
out
=0 mA; Address and control inputs
are STABLE (HIGH) during DESELECT; Data bus inputs are SWITCHING.
I
DD1
I
DD2P
I
DD2F
I
DD2Q
I
DD3P
I
DD3N
I
DD4R
I
DD4W
I
DD5B
I
DD5D
I
DD6
I
DD7
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