參數(shù)資料
型號: HY5DU561622DT-6
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 16M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝: 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66
文件頁數(shù): 15/28頁
文件大小: 814K
代理商: HY5DU561622DT-6
Rev. 0.6 / Mar. 2005
22
HY5DU561622DT
DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Speed
Unit
Note
5
6
Operating Current
IDD1
One bank; Active - Read - Precharge;
Burst Length=4; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once per clock
cycle; IOUT=0mA
150
mA
Precharge Power Down
Standby Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
20
mA
Idle Standby Current
IDD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs changing once
per clock cycle.
VIN=VREF for DQ, DQS and DM
70
mA
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode ; CKE=Low,
tCK=tCK(min)
30
mA
Active Standby Current
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per clock
cycle; Address and other control inputs changing
once per clock cycle
80
mA
Operating Current
IDD4R
Burst=2;Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
200
mA
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
mA
Auto Refresh Current
IDD5
tRC=tRFC(min); All banks active
180
mA
Self Refresh Current
IDD6
CKE=<0.2V; External clock on; tCK=tCK(min)
4mA
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