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參數(shù)資料
| 型號： | HUFA76413DK8T |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 功率晶體管 |
| 英文描述： | N-Channel Logic Level UltraFET Power MOSFET 60V, 4.8A, 56mз |
| 中文描述： | 5.1 A, 60 V, 0.049 ohm, 2 CHANNEL, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | SO-8 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 269K |
| 代理商： | HUFA76413DK8T |
2003 Fairchild Semiconductor Corporation
Rev. B
H
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
JM
, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
DM
, in an
application.
Therefore
the
temperature, T
A
(
o
C), and thermal resistance R
θ
JA
(
o
C/W)
must be reviewed to ensure that T
JM
is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
application’s
ambient
In using surface mount devices such as the SO-8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of P
DM
is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 22
defines the R
θ
JA
for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction
temperature
or
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
power
dissipation.
Pulse
Thermal resistances corresponding to other copper areas
can be obtained from Figure 22 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.
The dual die SO-8 package introduces an additional thermal
coupling resistance, R
θ
Equation 3 describes R
θ
B
as a
function of the top copper mouting pad area.
The thermal coupling resistance vs. copper area is also
graphically depicted in Figure 22.
(EQ. 1)
PDM
θ
JA
–
(
-----------------------------
)
=
(EQ. 2)
R
θ
JA
103.2
24.3
Area
(
)
ln
–
=
(EQ. 3)
R
θ
B
46.4
21.7
Area
(
)
ln
–
=
Figure 22. Thermal Resistance vs Mounting
Pad Area
0
0.001
50
100
150
200
250
300
0.01
0.1
1
R
θ
,
θ
J
(
o
C
AREA, TOP COPPER AREA (in
2
) PER DIE
191
o
C/W - 0.027in
2
228
o
C/W - 0.006in
2
R
θ
JA
= 103.2 - 24.3
*
ln
(AREA)
R
θβ
= 46.4 - 21.7
*
ln
(AREA)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HUFA76413DK8T | 制造商:Fairchild Semiconductor Corporation 功能描述:MOSFET |
| HUFA76413DK8T_10 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:N-Channel Logic Level UltraFET?? Power MOSFET 60V, 4.8A, 56m?? |
| HUFA76413DK8T_B76001A | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HUFA76413DK8T_F085 | 功能描述:MOSFET 60V Dual N-Channel Logic Level UltraFER RoHS:否 制造商:STMicroelectronics 晶體管極性:N-Channel 汲極/源極擊穿電壓:650 V 閘/源擊穿電壓:25 V 漏極連續(xù)電流:130 A 電阻汲極/源極 RDS（導(dǎo)通）:0.014 Ohms 配置:Single 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:Max247 封裝:Tube |
| HUFA76413P3 | 功能描述:MOSFET 20a 60V 0.056 Ohm Logic Level N-Ch RoHS:否 制造商:STMicroelectronics 晶體管極性:N-Channel 汲極/源極擊穿電壓:650 V 閘/源擊穿電壓:25 V 漏極連續(xù)電流:130 A 電阻汲極/源極 RDS（導(dǎo)通）:0.014 Ohms 配置:Single 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:Max247 封裝:Tube |
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