HT82J30R/HT82J30A
Rev. 1.00
8
December 20, 2006
read instruction has to be applied in both the main rou-
tine and the ISR, the interrupt is supposed to be dis-
abled prior to the table read instruction. It should not be
enabled until TBLH has been backed up. All table re-
lated instructions require two cycles to complete the
operation. These areas may function as normal pro-
gram memory depending upon the requirements.
Stack Register
STACK
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack is organized into 6 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction, RET or RETI, the pro-
gram counter is restored to its previous value from the
stack.Afterachipreset,theSPwillpointtothetopofthe
stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a CALL is sub-
sequently executed, stack overflow occurs and the first
entry will be lost as only the most recent 6 return ad-
dresses are stored.
Data Memory
RAM
The data memory is designed with 226 8 bits. The data
memory is divided into 2 functional groups: special func-
tion registers and general purpose data memory. Most
of them are read/write, but some are read only.
Reading any unused locations will return the result
00H . The general purpose data memory, addressed
from 28H to FFH, is used for data and control informa-
tion under instruction commands.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by SET [m].i and
CLR [m].i . They are also indirectly accessible through
the memory pointer registers MP.
Indirect Addressing Register
Location 00H is an indirect addressing register that is
not physically implemented. Any read/write operation of
[00H] accesses data memory pointed to by MP. Reading
location 00H itself indirectly will return the result 00H.
Writing indirectly results in no operation.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
Arithmetic and Logic Unit
ALU
This circuit performs 8-bit arithmetic and logic operations.
The ALU provides the following functions:
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
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