Pin Description
Pin Name
I/O
Options
Description
PA0~PA2
PA3/PFD
PA4/TMR
PA5/INT0
PA6/INT1
PA7
I/O
Pull-high*
Wake-up
PA3 or PFD
Bidirectional 8-bit input/output port. Each individual pin on this port can be config-
ured as a wake-up input by a configuration option. Software instructions deter-
mine if the pin is a CMOS output or Schmitt trigger input. Configuration options
determine which pin on this port have pull-high resistors. The PFD, TMR and ex-
ternalinterruptinputarepin-sharedwithPA3,PA4,andPA5,PA6,respectively.
PB0/AN0~
PB7/AN7
I/O
Pull-high*
Bidirectional 8-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt trigger input. Configuration options determine which pin
on this port have pull-high resistors. PB is pin-shared with the A/D input pins. The
A/D inputs are selected via software instructions Once selected as an A/D input,
the I/O function and pull-high resistor functions are disable automatically.
PB2, PB3 has CMOS or NMOS output option.
PC0/AN8~
PC7/AN15
I/O
Pull-high*
Bidirectional 8-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt trigger input. Configuration options determine which pin
on this port have pull-high resistors. PB is pin-shared with the A/D input pins. The
A/D inputs are selected via software instructions Once selected as an A/D input,
the I/O function and pull-high resistor functions are disabled automatically.
PD0/PWM0
PD1/SCS_A
PD2/SCK_A
PD3/SDI_A
PD4/SDO_A
PD5~PD6
PD7/SDO_B
I/O
Pull-high*
PD0 or PWM
Bi-directional 8-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt trigger input. Configuration options determine which pin
on this port have pull-high resistors. PD0 is pin-shared with the PWM output se-
lected via configuration option.
PD1~PD4 are pin-shared with SPI interface A.
PD4, PD7 have CMOS or NMOS output options.
PD7 is pin-shared with the SPI interface B.
PF0/SDI_B
PF1/SCK_B
PF2/SCS_B
I/O
Pull-high*
Bidirectional 3-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt trigger input. Configuration options determine which pin
on this port have pull-high resistors. PF0~PF2 is pin-shared with the SPI interface
B.
OSC1
OSC2
I
O
Crystal
or RC
OSC1 and OSC2 are connected to an external RC network or external crystal, de-
termined by configuration option, for the internal system clock. If the RC system
clock is selected, pin OSC2 can be used to measure the system clock at 1/4 sys-
tem frequency.
RES
I
Schmitt trigger reset input. Active low
VDD
Positive power supply
VSS
Negative power supply, ground
AVDD
Analog positive power supply
AVSS
Analog negative power supply
VREF
8-bit A/D reference voltage input pin
Note: * The pull-high resistors of each I/O port are controlled by options.
Absolute Maximum Ratings
Supply Voltage...........................V
SS
0.3V to V
SS
+6.0V
Storage Temperature............................ 50 C to 125 C
Input Voltage..............................V
SS
0.3V to V
DD
+0.3V
Operating Temperature...............................0 C to 70 C
I
OL
Total ..............................................................150mA
I
OH
Total............................................................ 100mA
Total Power Dissipation.....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
HT82J30R/HT82J30A
Rev. 1.00
3
December 20, 2006