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參數(shù)資料
| 型號： | HT82J30R |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 16 Channel A/D MCU with SPI Interface |
| 中文描述： | 16通道A / D轉(zhuǎn)換，SPI接口單片機 |
| 文件頁數(shù)： | 21/47頁 |
| 文件大?。?/td> | 312K |
| 代理商： | HT82J30R |
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HT82J30R/HT82J30A
Rev. 1.00
21
December 20, 2006
mentioned in the description.
Two corresponding registers, SBCR and SBDR are
unique to the serial interface and provide control, status,
and data storage.
SBCR_A, SBCR_B: Serial bus control register
Bit7 (CKS) clock source selection: f
SIO
=f
SYS
/4,
select as 0
Bit6(M1),Bit5(M0)master/slavemodeandbaudrate
selection
M1, M0: 00
MASTER MODE, BAUD RATE= f
SIO
MASTER MODE, BAUD RATE= f
SIO
/4
MASTER MODE, BAUD RATE= f
SIO
/16
SLAVE MODE
01
10
11
Bit4 (SBEN)
serial bus enable/disable (1/0)
Enable: (SCS dependent on CSEN bit)
Disable
(SCKB= 0 ) and waiting for writing data to SBDR
(TXRX buffer)
enable: SCK, SDI, SDO, SCS= 0
Master mode: write data to SBDR (TXRX buffer)
start transmission/reception automatically
Master mode: when the data has been transferred,
set TRF
Slave mode: when an SCK (and SCS dependent on
CSEN) is received, data in the TXRX buffer is
shifted-out and data on SDI is shifted-in.
Disable: SCK (SCK), SDI, SDO, SCS floating
Bit3(MLS)
MSBorLSB(1/0)shiftfirstcontrolbit
Bit2 (CSEN)
able (SCS), when CSEN=0, SCSB is floating.
serial bus selection signal enable/dis-
Bit1 (WCOL)
the SBDR register (TXRX buffer) when data is
transferred, writing will be ignored if data is written
to SBDR (TXRX buffer) when data is transferred.
this bit is set to 1 if data is written to
Bit0 (TRF)
used to generate an interrupt.
data transferred or data received
Note: data reception is still in operation when the
MCU enters the Power-down mode.
SBDR_A, SBDR_B: Serial bus data register
Data written to SBDR
only
write data to the TXRX buffer
Data read from SBDR
Operating Mode description:
Master transmitter: clock transmission and data I/O
started by writing to SBDR
MasterclocktransmissioninitiatedbywritingtoSBDR
Slave transmitter: data I/O started by clock reception
Slave receiver: data I/O started by clock reception
read from SBDR only
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SPI Serial Interface
There are two SPI interfaces, with each interface containing four basic signals and pins. These are SDI (serial data in-
put), SDO (serial data output), SCK (serial clock) and SCS (slave select pin). Note that each of these pin names will be
suffixedwitheitheranAorBtodenotewhichSCIinterfaceisbeingused,howevertominimiserepetition,thiswillnotbe
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