參數(shù)資料
型號(hào): HT82J30R
廠商: Holtek Semiconductor Inc.
英文描述: 16 Channel A/D MCU with SPI Interface
中文描述: 16通道A / D轉(zhuǎn)換,SPI接口單片機(jī)
文件頁數(shù): 12/47頁
文件大小: 312K
代理商: HT82J30R
HT82J30R/HT82J30A
Rev. 1.00
12
December 20, 2006
Power Down Operation
HALT
The HALT mode is initialized by the HALT instruction
and results in the following...
The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
The contents of the on chip RAM and registers remain
unchanged.
The WDT and WDT prescaler will be cleared and re-
sume counting again (if the WDT clock comes from
the WDT oscillator).
All of the I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
The system can leave the Power-down mode by means
of an external reset, an interrupt, an external falling
edge signal on port Aor a WDToverflow. An external re-
set causes a device initialization and the WDT overflow
performs a warm reset . After the TO and PDF flags
are examined, the reason for chip reset can be deter-
mined. The PDF flag is cleared by a system power-up or
executing the CLR WDT instruction and is set when
executing the HALT instruction. The TO flag is set if
the WDT time-out occurs, and causes a wake-up that
only resets the Program Counter and SP; the others re-
main in their original status.
The port A wake-up and interrupt methods of wake-up
can be considered as a continuation of normal execu-
tion. Each bit in port Acan be independently selected to
wake-up the device using configuration options. Awak-
ening from an I/O port stimulus, the program will resume
execution of the next instruction. If it awakens from an
interrupt, two sequences may occur. If the related inter-
rupt is disabled or the interrupt is enabled but the stack
is full, the program will resume execution at the next in-
struction. If the interrupt is enabled and the stack is not
full, the regular interrupt response takes place. If an in-
terrupt request flag is set to 1 before entering the
Power-down mode, the wake-up function of the related
interrupt will be disabled. Once a wake-up event occurs,
it takes 1024 t
SYS
(system clock period) to resume nor-
maloperation.Inotherwords,adummyperiodwillbein-
serted after a wake-up. If the wake-up results from an
interrupt acknowledge signal, the actual interrupt sub-
routine execution will be delayed by one or more cycles.
If the wake-up results in the next instruction execution,
this will be executed immediately after the dummy pe-
riod has finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the Power-down
mode.
Reset
There are three ways in which a reset can occur:
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
The WDT time-out during Power-down is different from
other chip reset conditions, since it can perform a warm
reset that resets only the Program Counter and SP,
leaving the other circuits in their original state. Some
registers remain unchanged during other reset condi-
tions. Most registers are reset to their initial condition
when the reset conditions are met. By examining the
PDF and TO flags, the program can distinguish be-
tween different chip resets .
TO
PDF
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: u stands for unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the Power-down mode.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from Power-down
will enable the SST delay.
Anextraoptionloadtimedelayisaddedduringasystem
reset (power-up, WDT time-out at normal mode or RES
reset).
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