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參數(shù)資料
| 型號： | HT48C06 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | Cost-Effective I/O Type 8-Bit MCU |
| 中文描述： | 成本效益的I / O型8位微控制器 |
| 文件頁數(shù)： | 11/38頁 |
| 文件大?。?/td> | 264K |
| 代理商： | HT48C06 |
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HT48R05A-1/HT48C05/HT48R06A-1/HT48C06
Rev. 1.10
11
June 9, 2004
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
WDTS Register
The WDT overflow under normal operation will initialize
chip reset and set the status bit TO . But in the HALT
mode, the overflow will initialize a warm reset , and
only the PC and SP are reset to zero. To clear the con-
tents of WDT (including the WDT prescaler), three
methods are adopted; external reset (a low level to
RES), software instruction and a
HALT
instruction.
The software instruction include
CLR WDT and the
other set
two types of instruction, only one can be active depend-
CLR WDT1 and CLR WDT2 . Of these
ing on the option
CLR WDT times selection option . If
the CLR WDT is selected (i.e. CLRWDT times equal
one), any execution of the CLR WDT instruction will
clear the WDT. In the case that CLR WDT1 and CLR
WDT2
these two instructions must be executed to clear the
WDT; otherwise, the WDTmay reset the chip as a result
of time-out.
are chosen (i.e. CLRWDT times equal two),
Power Down Operation
HALT
The HALT mode is initialized by the HALT instruction
and results in the following...
The system oscillator will be turned off but the WDT
oscillator keeps running (if the WDT oscillator is se-
lected).
The contents of the on chip RAM and registers remain
unchanged.
WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).
AlloftheI/Oportsmaintaintheiroriginalstatus.
The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDToverflow per-
forms a warm reset . After the TO and PDF flags are
examined, the reason for chip reset can be determined.
The PDF flag is cleared by system power-up or execut-
ing the CLR WDT instruction and is set when execut-
ing the HALT instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the PC and SP; the others keep their original status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by the options. Awakening from an I/O port stim-
ulus, the program will resume execution of the next in-
struction. If it is awakening from an interrupt, two
sequences may happen. If the related interrupt is dis-
abled or the interrupt is enabled but the stack is full, the
program will resume execution at the next instruction. If
theinterruptisenabledandthestackisnotfull,theregu-
lar interrupt response takes place. If an interrupt request
flag is set to 1 before entering the HALT mode, the
wake-upfunctionoftherelatedinterruptwillbedisabled.
Once a wake-up event occurs, it takes 1024 t
SYS
(sys-
tem clock period) to resume normal operation. In other
words, a dummy period will be inserted after wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset can occur:
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm re -
set thatresetsonlythePCandSP,leavingtheothercir-
cuits in their original state. Some registers remain un-
changed during other reset conditions. Most registers
are reset to the initial condition when the reset condi-
tions are met. By examining the PDF and TO flags, the
programcandistinguishbetweendifferent chipresets .
TO PDF
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: u means unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
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