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參數(shù)資料
| 型號： | HT46R221 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit A/D Type MCU |
| 中文描述： | 8位A / D型微控制器 |
| 文件頁數(shù)： | 17/46頁 |
| 文件大小： | 390K |
| 代理商： | HT46R221 |
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HT46R22/HT46C22
Rev. 1.10
17
October 2, 2002
A (6+2) bits mode PWM cycle is divided into four modu-
lation cycles (modulation cycle 0~modulation cycle 3).
Each modulation cycle has 64 PWM input clock period.
In a (6+2) bit PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.2.
The group 2 is denoted by AC which is the value of
PWM.1~PWM.0.
In a (6+2) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
AC (0~3)
Duty Cycle
Modulation cycle i
(i=0~3)
i<AC
DC
1
64
i AC
DC
64
A (7+1) bits mode PWM cycle is divided into two modu-
lation cycles (modulation cycle0~modulation cycle 1).
Eachmodulationcyclehas128PWMinputclockperiod.
In a (7+1) bits PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.1.
The group 2 is denoted by AC which is the value of
PWM.0.
In a (7+1) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
AC (0~1)
Duty Cycle
Modulation cycle i
(i=0~1)
i<AC
DC
1
128
i AC
DC
128
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
PWM
Modulation Frequency
PWM Cycle
Frequency
PWM Cycle
Duty
F
SYS
/64 for (6+2) bits mode
F
SYS
/128for(7+1)bitsmode
f
SYS
/256
[PWM]/256
A/D converter
The 8 channels and 9-bit resolution A/D (8-bit accuracy)
converter are implemented in this microcontroller. The
reference voltage is VDD. The A/D converter contains 4
special registers which are; ADRL (24H), ADRH (25H),
ADCR (26H) and ACSR (27H). The ADRH and ADRL
are A/D result register higher-order byte and
lower-order byte and are read-only. After the A/D con-
version is completed, the ADRH and ADRL should be
read to get the conversion result data. The ADCR is an
A/D converter control register, which defines the A/D
channel number, analog channel select, start A/D con-
version control bit and the end of A/D conversion flag. If
the users want to start an A/D conversion. Define PB
configuration, select the converted analog channel, and
give START bit a raising edge and falling edge
(0
cleared and an A/D converter interrupt occurs (if the A/D
converter interrupt is enabled). The ACSR is A/D clock
setting register, which is used to select the A/D clock
source.
1
0). At the end of A/D conversion, the EOC bit is
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the ADCR are used to
select an analog input channel. There are a total of eight
channels to select. The bit5~bit3 of the ADCR are used
to set PB configurations. PB can be an analog input or
as digital I/O line decided by these 3 bits. Once a PB line
is selected as an analog input, the I/O functions and
pull-high resistor of this I/O line are disabled and the A/D
converter circuit is power on. The EOC bit (bit6 of the
ADCR) is end of A/D conversion flag. Check this bit to
know when A/D conversion is completed. The START
bit of the ADCR is used to begin the conversion of the
A/D converter. Giving START bit a rising edge and fall-
ing edge means that the A/D conversion has started. In
order to ensure the A/D conversion is completed, the
START should remain at 0 until the EOC is cleared to
0 (end of A/D conversion).
The bit 7 of the ACSR is used for testing purposes only.
It can not be used by the users. The bit1 and bit0 of the
ACSR are used to select A/D clock sources.
Label
(ACSR)
Bits
Function
ADCS0
ADCS1
0
1
Selects the A/D converter clock
source
00= system clock 2
01= system clock 8
10= system clock 32
11= undefined
2~6 Unused bit, read as 0
TEST
7
For test mode used only
ACSR register
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