參數(shù)資料
型號: HSP50215EVAL
廠商: Intersil Corporation
英文描述: DSP Modulator Evaluation Board
中文描述: DSP的調(diào)制器評估板
文件頁數(shù): 21/21頁
文件大小: 157K
代理商: HSP50215EVAL
3-442
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
Waveforms
FIGURE 17. TIMING RELATIVE TO WR OR WITH CE
FIGURE 18. OUTPUT RISE AND FALL TIMES
NOTE: CASZ, OFM, OE are signals that must remain constant with
respect to REFCLK until the part is reset. In the write mode,
either CE or WR must be clocked while the other is tied low.
In read mode, either CE or RD must be clocked while the oth-
er is tied low. Never tie all three interface signals (CE, RD and
WR) low at the same time.
FIGURE 19. TIMING RELATIVE TO REFCLK
FIGURE 20. OUTPUT ENABLE/DISABLE
FIGURE 21. TIMING RELATIVE TO READ OR TO CE
WR OR-ED CE
A9-0
t
AS
t
AH
t
WRH
t
WRL
t
WF
FIFORDY
t
CS
t
CH
C15-0
t
RF
t
RF
0.8V
2.0V
t
DOC
REFCLK
CAS(15:0),
SYNCIN
t
DS
t
DH
t
CL
t
CH
t
CP
SAMPCLK, SYNCOUT,
FIFORDY
t
DO
OUT(15:0)
t
RDO
C15-0
t
ROD
t
RL
RD OR’ed CE
A9-0
t
ADO
1.7V
1.3V
1.5V
1.5V
t
OE
t
OD
OUT(15:0)
OE
HSP50215
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