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參數(shù)資料
| 型號： | HSP50215EVAL |
| 廠商： | Intersil Corporation |
| 英文描述： | DSP Modulator Evaluation Board |
| 中文描述： | DSP的調(diào)制器評估板 |
| 文件頁數(shù)： | 16/21頁 |
| 文件大?。?/td> | 157K |
| 代理商： | HSP50215EVAL |
3-437
Configuration Control Register Bit Definitions
CONTROL ADDRESS 0: I CHANNEL INPUT
BIT
POSITION
FUNCTION
DESCRIPTION
15-0
I Channel QASK Input or
FM Input
IIN(15:0). In QASK mode, this is the I input vector. The format is 2’s complement. The MSB is bit 15.
The mixer operation is:
OUT = (I*COS) - (Q*SIN).
In FM mode, this is interpreted as an offset frequency to the center frequency. The modulation index
depends on the mode and the filter coefficients. In FM with post filter mode, the phase change per
input sample can range from -180 to 180 degrees, so the deviation is limited to
±
(input sample rate)/2.
CONTROL ADDRESS 1: Q CHANNEL INPUT
BIT
POSITION
FUNCTION
DESCRIPTION
15-0
Q Channel Input
QIN(15:0). In QASK mode, this is the Q input vector. See address 0 above. In FM mode, this input is
not used.
CONTROL ADDRESS 2: TIMING NCO FREQUENCY MSBYTE CONTROL WORD
BIT
POSITION
FUNCTION
DESCRIPTION
15-14
Reserved (Note 1)
Reserved (Note 1).
13-0
Sample Rate Ratio’s
Most Significant 14 Bits
SR(29:16). The sample rate is controlled by a 30-bit NCO clocked at the output clock rate. The upper
MSByte of the sample rate ratio SR(29:0), or SR(29:16), is loaded in this address. The sample rate is
computed by the formula:
F
RESAMP
= SR(29:0) x f
CLK
x 2
-32
; SR (29:0) = INT[(F
RESAMP
/f
CLK
) X 2
32
].
CONTROL ADDRESS 3: TIMING NCO FREQUENCY LSBYTE CONTROL WORD
BIT
POSITION
FUNCTION
DESCRIPTION
15-0
Sample Rate Ratio’s
Least Significant 16 Bits
SR(15:0). See Control Address 2. SR(15:0) is loaded in this address.
CONTROL ADDRESS 4: CARRIER CENTER FREQUENCY MSBYTE CONTROL WORD
BIT
POSITION
FUNCTION
DESCRIPTION
15-0
Carrier Center
Frequency’s Most
Significant 16 Bits
CF(31:16). The SIN/COS ROM is controlled by a 32-bit NCO clocked at the input clock rate. The upper
MSByte of the sample rate ratio CF(31:0), or CF(31:16), is loaded in this address. The center frequen-
cy is computed by the formula:
f
C
= CF(31:0) x f
CLK
x 2
-32
; CF(31:0) = INT(f
C
/f
CLK
X 2
32
). Setting CW 4 and 5 to zero bypasses the
mixers (COS = 1; SIN = 0).
CONTROL ADDRESS 5: CARRIER CENTER FREQUENCY LSBYTE CONTROL WORD
BIT
POSITION
FUNCTION
DESCRIPTION
15-0
Carrier Center
Frequency’s Least
Significant 16 Bits
CF(15:0). See Control Address 4. CF(15:0) is loaded in this address. Setting CW 4 and 5 to zero by-
passes the mixers (COS = 1; SIN = 0).
CONTROL ADDRESS 16: MODULATION CONTROL
BIT
POSITION
FUNCTION
DESCRIPTION
15-4
Reserved (Note 1)
Reserved (Note 1).
3
Enable Output
EN OUT.
HSP50215
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PDF描述 |
|---|---|
| HSP50215 | Digital UpConverter(數(shù)字上變頻器) |
| HSP50216 | Four-Channel Programmable Digital DownConverter(四通道可編程數(shù)字下變頻器) |
| HSP50307 | Burst QPSK Modulator(混合信號QPSK調(diào)制器) |
| HSP50415VI | CABLE ASSEMBLY; 75 OHM TNC MALE TO 75 OHM TNC MALE; 75 OHM, RG6A/U COAX |
| HSP50415EVAL1 | HSP50415EVAL1 Evaluation Kit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50215VC | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital UpConverter |
| HSP50215VI | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital UpConverter |
| HSP50216 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Four-Channel Programmable Digital Downconverter |
| HSP50216_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Four-Channel Programmable Digital DownConverter |
| HSP50216_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Four-Channel Programmable Digital Downconverter |
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