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參數(shù)資料
| 型號(hào)： | HSP50214VI |
| 廠商： | INTERSIL CORP |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Programmable Downconverter |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP120 |
| 封裝： | MQFP-120 |
| 文件頁(yè)數(shù)： | 47/54頁(yè) |
| 文件大小： | 395K |
| 代理商： | HSP50214VI |
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47
CONTROL WORD 20: BUFFER RAM, DIRECT PARALLEL, AND DIRECT SERIAL OUTPUT CONFIGURATION
(SYNCHRONIZED WITH PROCCLK)
BIT
POSITION
FUNCTION
DESCRIPTION
31-26
Reserved
Reserved.
25
Data Source for
Least Significant
Bytes of AOUT and
BOUT
Output LSBytes, bits (7:0), of AOUT and BOUT can provide:
0- Buffer RAM Mode Output or.
1- Parallel Direct Mode Output.
24
Buffered Output
Mode Interface
Buffered Mode Output interfaces to either:
0- 8-bit
μ
P (address =
μ
P ASEL(5:#); CLK =
μ
P RAM read).
1- 16-bit
μ
P (address = SEL(2:0); CLK = OEBL).
23-22
AOUT Direct Parallel
Output Mode Data
Source
The data word sent by the Direct Parallel Output Mode to AOUT is:
00- I Data.
01- Magnitude.
1X- Frequency.
21-20
BOUT Direct Parallel
Output Mode Data
Source
The data word sent by the Direct Parallel Output Mode to BOUT is:
00- Q Data.
01- Phase.
1X- Magnitude.
19
Serial Output Sync
Polarity
0- Normal Sync Mode (active high).
1- Sync Inverted (active low).
18
Serial Output Clock
Polarity
0- Output Clock Inverted rising edge aligns with data transitions.
1- Output Clock Normal falling edge aligns with data transitions.
17
Serial Output Sync
Position
0- Sync is asserted one bit time after the last bit of the serial word (Late Mode).
1- Sync is asserted one bit time prior to the first bit of the serial word (Early Mode).
16-14
Serial Out Clock
Divider
000- Serial Output at PROCCLK/16.
001- Serial Output at PROCCLK/8.
010- Serial Output at PROCCLK/4.
011- Serial Output at PROCCLK/2.
1XX- Serial Output at PROCCLK rate.
13-12
I Data Serial Output
Tag Bit
00- No Tag Bit. LSB of word is passed.
01- 0 Tag Bit. LSB of word is set to zero.
1X- 1 Tag Bit. LSB of word is set to one.
11-10
Q Data Serial Output
Tag Bit
(See I Data Serial Output Tag Selection above).
9-8
Magnitude Data Se-
rial Output Tag Bit
(See I Data Serial Output Tag Selection above).
7-6
Phase Data Serial
Output Tag Bit
(See I Data Serial Output Tag Selection above).
5-4
Frequency Data Se-
rial Output Tag Bit
(See I Data Serial Output Tag Selection above).
3-2
AGC Data Serial
Output Tag Bit
(See I Data Serial Output Tag Selection above).
0
1
HSP50214
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP50214 | Programmable Downconverter |
| HSP50215VC | Digital UpConverter |
| HSP50215VI | Digital UpConverter |
| HSP50215EVAL | DSP Modulator Evaluation Board |
| HSP50215 | Digital UpConverter(數(shù)字上變頻器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50215 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215EVAL | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215VC | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Digital UpConverter |
| HSP50215VI | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Digital UpConverter |
| HSP50216 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Four-Channel Programmable Digital Downconverter |
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