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參數(shù)資料
| 型號： | HSP50214VI |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Programmable Downconverter |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP120 |
| 封裝： | MQFP-120 |
| 文件頁數(shù)： | 42/54頁 |
| 文件大?。?/td> | 395K |
| 代理商： | HSP50214VI |
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42
CONTROL WORD 7: HB, FIR CONFIGURATION (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
FUNCTION
DESCRIPTION
31-22
Reserved
Reserved.
21
Enable External
Filter Sync
0- The SYNCIN2 pin has no effect on the halfband and FIR filters.
1- When the SYNCIN2 pin is asserted, the filter control circuitry in the halfband filters, the FIR,
the resampler, and the discriminator are reset. SYNCIN2 can be used to synchronize the com-
putations of the filters in multiple parts for the alignment. See Synchronization Section.
20
Halfband (HB)
Bypass
1- Bypass Halfband Filters.
0- Enable HB Filters (at least one HB must be enabled).
19
HB5 Enable
0- Disables HB number 5 (the last in the cascade).
1- Enables HB filter number 5.
18
HB4 Enable
Setting this bit enables HB filter number 4.
17
HB3 Enable
Setting this bit enables HB filter number 3.
16
HB2 Enable
Setting this bit enables HB filter number 2.
15
HB1 Enable
Setting this bit enables HB filter number 1.
14-11
FIR Decimation
Load decimation from 1-16, where 0000 = 16. Bit 14 is the MSB.
10
FIR Real/Complex
0- Complex Filter.
1- Dual Real Filters.
9
FIR Sym Type
0- Odd Symmetry.
1- Even Symmetry.
8
FIR Symmetry
0- Symmetric Filters.
1- Asymmetric Filters.
7-0
FIR Taps
Number of taps in the FIR filter. Range is 1 to 255, where 0000000 is invalid.
CONTROL WORD 8: AGC CONFIGURATION 1 (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
FUNCTION
DESCRIPTION
31-30
Reserved
Reserved.
29
Sync AGC Updates
to SYNCIN2
When this bit is 1, the SYNCIN2 pin loads the contents of the master registers into the AGC
accumulator.
28-16
Threshold
The magnitude measurement out of the cartesian to polar converter is subtracted from this val-
ue to get the gain error. A gain of 1.647 in the cartesian to polar conversion that must be taken
into account when computing this threshold. These bits are weighted -2
2
down to 2
-10
. Bit 28 is
the MSB.
15-12
Loop Gain 1
Mantissa
Selected when AGCGNSEL = 1. These bits, MMMM, together with the exponent bits, EEEE
(11-8), set the loop gain for the AGC loop. The gain adjustment per output sample is:
1.5dB(Threshold -[Magnitude * 1.6]) 0.MMMM * 2
-(15 - EEEE)
where magnitude ranges from 0
to 1.414 and the threshold is programmed in bits 28-16. The decimal value for the mantissa is
calculated as DEC(MMMM)/16. Bit 15 is the MSB.
11-8
Loop Gain 1
Exponent
Selected when AGCGNSEL = 1. These bits are EEEE. See description of bits 15-12. Bit 11 is
the MSB.
HSP50214
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PDF描述 |
|---|---|
| HSP50214 | Programmable Downconverter |
| HSP50215VC | Digital UpConverter |
| HSP50215VI | Digital UpConverter |
| HSP50215EVAL | DSP Modulator Evaluation Board |
| HSP50215 | Digital UpConverter(數(shù)字上變頻器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50215 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215EVAL | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215VC | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital UpConverter |
| HSP50215VI | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital UpConverter |
| HSP50216 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Four-Channel Programmable Digital Downconverter |
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