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參數(shù)資料
| 型號(hào)： | HS1-80C85RH-Q |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Radiation Hardened 8-Bit CMOS Microprocessor |
| 中文描述： | 8-BIT, 2 MHz, MICROPROCESSOR, CDIP40 |
| 封裝： | SIDE BRAZED, METAL SEALED, CERAMIC, DIP-40 |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大小： | 758K |
| 代理商： | HS1-80C85RH-Q |
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12
HS-80C85RH Caveats
1. An important caveat that is applicable to CMOS devices
in general is that unused inputs should never be left
floating. This rule also applies to inputs connected to a
three-state bus. The need for external pull-up resistors
during three-state bus conditions is eliminated by the
presence of regenerative latches on the following
HS-80C85RH output pins: AD0-AD7, A8-A15, and IO/M.
Figure 10 depicts an output and corresponding
regenerative latch. When the output driver assumes the
high impedance state, the latch holds the bus in whatever
logic state (high or low) it was before the three-state
condition. A transient drive current of approximately
±
1.0mA at 0.5VDD for 10ns is required to switch the
latch. Thus, CMOS device inputs connected to the bus
are not allowed to float during three-state conditions.
2. The RD and WR pins of the HS-80C85RH contain internal
dynamic pull-up transistors to avoid spurious selection of
memory devices when the RD and WR pins assume the
high impedance state. This eliminates the need for
external resistive pull-ups on these pins.
3. The RESET IN and X1 inputs on the HS-80C85RH are
schmit trigger inputs. This eliminates the possibility of
internal oscillations in response to slow rise time input
signals at these pins.
4. A high frequency bypass capacitor of approximately
0.1
μ
F should be connected between VDD and GND to
shunt power supply transients.
5. The HS-80C85RH is functional within 10 input clock
cycles after application of power (assuming that reset has
been asserted from power-on). Start up conditions in the
crystal controlled oscillator mode must also account for
the characteristics of the oscillator.
Generating An HS-80C85RH Wait State
If your system requirements are such that slow memories or
peripheral devices are being used, the circuit shown in
Figure 11 may be used to insert one WAIT state in each
HS-80C85RH machine cycle.
The D flip-flops should be chosen so that:
1. CLK is rising edge-triggered
2. CLEAR is low-level active
The READY line is used to extend the read and write pulse
lengths so that the 80C85RH can be used with slow
memory. HOLD causes the CPU to relinquish the bus when
it is through with it by floating the Address and Data Buses.
System Interface
The HS-80C85RH family includes memory components,
which are directly compatible to the HS-8OC8SRH CPU. For
example, a system consisting of the three radiation-
hardened chips, HS-80C85RH, HS-81C56RH, and
HS-83C55RH will have the following features:
1. 2K Bytes ROM
2. 256 Bytes RAM
3. 1 Timer/Counter
4. 4 8-bit I/O Ports
5. 1 6-bit I/O Port
6. 4 Interrupt Levels
7. Serial In/Serial Out Ports
This minimum system, using the standard I/O technique is
as shown in Figure 12.
In addition to standard 1/0, the memory mapped I/O offers
an efficient I/O addressing technique. With this technique, an
area of memory address space is assigned for I/O address,
thereby, using the memory address for I/O manipulation.
Figure 13 shows the system configuration of Memory
Mapped I/O using HS-80C85RH.
The HS-80C85RH CPU can also interface with the standard
radiation-hardened memory that does not have the
multiplexed address/data bus. It will require use of the
HS-82C12RH (8-bit latch) as shown in Figure 14.
FIGURE 10. OUTPUT DRIVER AND LATCH FOR PINS
AD0-AD7, A8-A15 AND IO/M
OUTPUT
DRIVER
REGENERATIVE
LATCH
OUTPUT
PIN
NOTE: ALE and CLK (OUT) should be buffered if CLK input of latch
exceeds 80C85RH IOL or IOH.
FIGURE 11. GENERATION OF A WAIT STATE FOR
HS-80C85RH CPU
CLEAR
CLK
“D”
F/F
D
ALE
VDD
80C85RH
CLK
OUTPUT
Q
TO
80C85RH
READY
INPUT
CLK
“D”
F/F
D
Q
(NOTE)
HS-80C85RH
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HS1-81C55RH-8 | Radiation Hardened 256 x 8 CMOS RAM |
| HS1-81C55RH-Q | Radiation Hardened 256 x 8 CMOS RAM |
| HS1-81C56RH-8 | Radiation Hardened 256 x 8 CMOS RAM |
| HS1-81C56RH-Q | Radiation Hardened 256 x 8 CMOS RAM |
| HS1100 | RELATIVE HUMIDITY SENSOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HS1-80C86RH | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened 16-Bit CMOS Microprocessor |
| HS1-80C86RH/PROTO | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| HS1-80C86RH-8 | 制造商:Intersil Corporation 功能描述:MPU 16BIT CMOS 5MHZ 40PIN SBCDIP - Rail/Tube |
| HS1-80C86RH-Q | 制造商:Intersil Corporation 功能描述:MPU 16BIT CMOS 5MHZ 40PIN SBCDIP - Rail/Tube |
| HS18135 | 制造商:Microsemi Corporation 功能描述:POWER MODULE - DIODE - Bulk |
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