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參數(shù)資料
| 型號： | HS1-81C56RH-Q |
| 廠商： | INTERSIL CORP |
| 元件分類： | DRAM |
| 英文描述： | Radiation Hardened 256 x 8 CMOS RAM |
| 中文描述： | 256 X 8 MULTI-PORT SRAM, CDIP40 |
| 封裝： | SIDE BRAZED, CERAMIC, DIP-40 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 122K |
| 代理商： | HS1-81C56RH-Q |
1
TM
File Number
3039.2
HS-81C55RH, HS-81C56RH
Radiation Hardened 256 x 8 CMOS RAM
The HS-81C55/56RH are radiation hardened RAM and I/O
chips fabricated using the Intersil radiation hardened Self-
Aligned Junction Isolated (SAJI) silicon gate technology.
Latch-up free operation is achieved by the use of epitaxial
starting material to eliminate the parasitic SCR effect seen in
conventional bulk CMOS devices.
The HS-81C55/56RH is intended for use with the
HS-80C85RH radiation hardened microprocessor system.
The RAM portion is designed as 2048 static cells organized
as 256 x 8. A maximum post irradiation access time of
500ns allows the HS-81C55/56RH to be used with the
HS-80C85RH CPU without any wait states. The
HS-81C55RH requires an active low chip enable while the
HS-81C56RH requires an active high chip enable. These
chips are designed for operation utilizing a single 5V power
supply.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-96766. A “hot-link” is provided
on our homepage for downloading.
http://www.intersil.com/spacedefense/space.asp
Features
Electrically Screened to SMD # 5962-96766
QML Qualified per MIL-PRF-38535 Requirements
Radiation Hardened EPI-CMOS
- Total Dose. . . . . . . . . . . . . . . . . . . . .100 krad(Si) (Max)
- Transient Upset. . . . . . . . . . . . . . . . . .>1 x 10
8
rad(Si)/s
- Latch-Up Free. . . . . . . . . . . . . . . . . .>1 x 10
12
rad(Si)/s
Electrically Equivalent to Sandia SA 3001
Pin Compatible with Intel 8155/56
Bus Compatible with HS-80C85RH
Single 5V Power Supply
Low Standby Current . . . . . . . . . . . . . . . . . . . .200
μ
A Max
Low Operating Current. . . . . . . . . . . . . . . . . . . .2mA/MHz
Completely Static Design
Internal Address Latches
Two Programmable 8-Bit I/O Ports
One Programmable 6-Bit I/O Port
Programmable 14-Bit Binary Counter/Timer
Multiplexed Address and Data Bus
Self Aligned Junction Isolated (SAJI) Process
Military Temperature Range. . . . . . . . . . . -55
o
C to 125
o
C
Functional Diagram
Ordering Information
ORDERING NUMBER
INTERNAL
MKT. NUMBER
TEMP. RANGE
(
o
C)
5962R9676601QXC
HS1-81C55RH-8
-55 to 125
5962R9676601QYC
HS9-81C55RH-8
-55 to 125
5962R9676601VXC
HS1-81C55RH-Q
-55 to 125
5962R9676601VYC
HS9-81C55RH-Q
-55 to 125
5962R9676602QXC
HS1-81C56RH-8
-55 to 125
5962R9676602QYC
HS9-81C56RH-8
-55 to 125
5962R9676602VXC
HS1-81C56RH-Q
-55 to 125
5962R9676602VYC
HS9-81C56RH-Q
-55 to 125
256 x 8
STATIC
RAM
A
B
C
TIMER
IO/M
AD0 - AD7
CE OR CE
ALE
RD
WR
RESET
TIMER CLK
TIMER OUT
8
PA0 - PA7
PORT A
8
PB0 - PB7
PORT B
8
PC0 - PC5
PORT C
VDD (10V)
GND
81C55RH = CE
81C56RH = CE
Data Sheet
August 2000
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright Intersil Corporation 2000
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