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參數(shù)資料
| 型號： | HS1-80C85RH-Q |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Radiation Hardened 8-Bit CMOS Microprocessor |
| 中文描述： | 8-BIT, 2 MHz, MICROPROCESSOR, CDIP40 |
| 封裝： | SIDE BRAZED, METAL SEALED, CERAMIC, DIP-40 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 758K |
| 代理商： | HS1-80C85RH-Q |
11
the TRAP interrupt request circuitry within the HS-80C85RH.
Note that the servicing of any interrupt (TRAP, RST 7.5, RST
6.5, RST 5.5, INTR) disables all future interrupts (except
TRAPs) until an EI instruction is executed.
The TRAP interrupt is special in that is disables interrupts, but
preserves the previous interrupt enable status. Perform- ing
the first RIM instruction following a TRAP interrupt allows you
to determine whether interrupts were enabled or disabled
prior to the TRAP. All subsequent RIM instructions provide
current interrupt enable status. Performing a RIM instruction
following INTR, or RST 5.5-7.5 will provide current interrupt
enable status, revealing that interrupts are disabled.
The serial I/O system is also controlled by the RIM and SIM
instructions. SID is read by RIM, and SIM sets the SOD data.
Driving the X1 and X2 Inputs
You may drive the clock inputs of the HS-80C85RH with a
crystal, an LC tuned circuit, an RC network, or an external clock
source. The driving frequency may be any value from DC to
4MHz and must be twice the desired internal clock frequency.
The following guidelines should be observed when a crystal
is used to drive the HS-80C85RH clock input:
1. A 20pF capacitor should be connected from X2 to ground
to assure oscillator start-up at the correct frequency.
2. A 10M
resistor is required between X1 and X2 for bias
point stabilization. In addition, the crystal should have the
following characteristics:
1) Parallel resonance at twice the desired internal clock
frequency
2) CL (load capacitance)
≤
30pF
3) CS (shunt capacitance)
≤
7pF
4) RS (equivalent shunt resistance)
≤
75
5) Drive level: 10mW
6) Frequency tolerance:
±
0.005% (suggested)
A parallel-resonant LC circuit may be used as the frequency-
determining network for the HS-80C85RH, providing that its
frequency tolerance of approximately
±
10% is acceptable.
The components are chosen from the formula:
2
π
L Cext
Cint
+
)
To minimize variations in frequency, it is recommended that
you choose a value for Cext that is at least twice that of Cint,
or 30pF. The use of an LC circuit is not recommended for
frequencies higher than approximately 4MHz.
An RC circuit may be used as the frequency-determining
network for the HS-80C85RH if maintaining a precise clock
frequency is of no importance. Variations in the on-chip timing
generation can cause a wide variation in frequency when
using the RC mode. Its advantage is its low component cost.
The driving frequency generated by the circuit shown is
approximately 3MHz. It is not recommended that frequencies
greatly higher or lower than this be attempted.
Figure 9 shows the recommended clock driver circuits.
For driving frequencies up to and including 4MHz you may
supply the driving signal to X1 and leave X2 open-circuited
(Figure 9D).
VDD
RESET IN
TRAP
EXTERNAL
TRAP
INTERRUPT
REQUEST
TRAP
INTERRUPT
REQUEST
INTERNAL
TRAP
ACKNOWLEDGE
INSIDE THE
80C85RH
SCHMITT
TRIGGER
CLEAR
TRAP F.F.
CLK
D
F/F
D
Q
RESET
FIGURE 8. TRAP AND RESET IN CIRCUIT
f
----------------------------------------------------
=
FIGURE 9A. QUARTZ CRYSTAL CLOCK DRIVER
FIGURE 9B. RC CIRCUIT CLOCK DRIVER
FIGURE 9C. LC TUNED CIRCUIT CLOCK DRIVER
NOTE: X2 Left Floating.
FIGURE 9D. 0-4MHz INPUT FREQUENCY EXTERNAL CLOCK
DRIVER CIRCUIT
FIGURE 9. CLOCK DRIVER CIRCUITS
20pF
REXT =
10M
X2
X1
1
2
CINT =
15pF
80C85RH
20pF
-6K
X2
X1
1
2
80C85RH
CEXT
X2
X1
1
2
CINT =
15pF
80C85RH
LEXT
X2
X1
LOW TIME > 60ns
(NOTE)
HS-80C85RH
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