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參數(shù)資料
| 型號： | HMS77C1001A |
| 廠商： | Hynix Semiconductor Inc. |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 40/45頁 |
| 文件大?。?/td> | 549K |
| 代理商： | HMS77C1001A |
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HMS77C1000A/HMS77C1001A
Oct. 2001 Ver. 2.0
37
15. WATCHDOG TIMER (WDT)
The Watchdog Timer (WDT) is a free running on-chip RC
oscillator which does not require any external components.
This RC oscillator is separate from the RC oscillator of the
X
IN
pin. That means that the WDT will run even if the
clock on the X
IN
and X
OUT
pins have been stopped, for ex-
ample, by execution of a SLEEP instruction. During nor-
mal operation or SLEEP, a WDT reset or wake-up reset
generates a device RESET.
The TO bit (STATUS<4>) will be cleared upon a Watch-
dog Timer reset.
The WDT can be permanently disabled by programming
the configuration bit WDTE as a '0' (Figure 12-2). Refer to
the HMS77C100XA Programming Specifications to deter-
mine how to access the configuration word.
15.1 WDT Period
The WDT has a nominal time-out period of 14 ms, (with
no prescaler). If a longer time-out period is desired, a pres-
caler with a division ratio of up to 1:256 can be assigned to
the WDT (under software control) by writing to the OP-
TION register. Thus, time-out a period of a nominal 3.5
seconds can be realized. These periods vary with tempera-
ture, V
DD
and part-to-part process variations (see DC
specs).
Under worst case conditions (V
DD
= Min., Temperature =
Max., max. WDT prescaler), it may take several seconds
before a WDT time-out occurs.
15.2 WDT Programming Considerations
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device RESET.
The SLEEP instruction resets the WDT and the postscaler,
if assigned to the WDT. This gives the maximum SLEEP
time before a WDT wake-up reset.
FIGURE 15-1 WATCHDOG TIMER BLOCK DIAGRAM
Name
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Power-On
Reset
RESET and
WDT Reset
OPTION
N/A
LOWOPT
PFDEN
T0CS
T0SE
PSA
PS2
PS1
PS0
0011 1111
0011 1111
TABLE 15-1 SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Postscaler
8
1
0
PSA
MUX
8 - to - 1 MUX
8-bit asynchronous
ripple counter
clear
MUX
PS2:PS0
PSA
1
0
WDT Time-Out
To TMR0
From TMR0 Clock Source
on-chip
RC-OSC
Watchdog Timer
enable
WDTE
SLEEP
clearing WDT
SLEEP
clearing WDT
PSA
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