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參數(shù)資料
| 型號： | HMS77C1001A |
| 廠商： | Hynix Semiconductor Inc. |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 23/45頁 |
| 文件大?。?/td> | 549K |
| 代理商： | HMS77C1001A |
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HMS77C1000A/HMS77C1001A
20
Oct. 2001 Ver. 2.0
9.3.2 TMR0 Register
The TMR0 register is a data register for 8-bit timer/
counter. In reset state, the TMR0 register is initialized with
“00
H
”.
9.3.3 Program Counter (PC)
The program counter contains the 10-bit address of the in-
struction to be executed(9-bit address for
HMS77C1000A).
The lower 8 bits of the program counter are contained in
the PCL register which can be provided by the instruction
word for a call instruction, or any instruction where the
PCL is the destination while the ninth bit of the program
counter comes from the page address bit - PA0 of the STA-
TUS register(HMS77C1001A only).
This is necessary to cause program branches across pro-
gram memory page boundaries.
Prior to the execution of a branch operation, the user must
initialize the PA0 bit of STATUS register.
The eighth bit of the program counter can come from the
instruction word by execution of goto instruction, or can be
cleared by execution of call or any instruction where the
PCL is the destination.
In reset state, the program counter is initialized with
“1FF
H
”(HMS77C1000A) or “3FF
H
”(HMS77C1001A).
Note:
Because PC<8> is cleared in the subroutine call
in-
struction, or any Modify PCL instruction, all subrou-
tine calls or computed jumps are limited to the first
256 locations of any program memory page (512
words long).
9.3.4 Stack Operation
The HMS77C100XA have a 2-level hardware stack. The
stack register consists of two 9-bit save regis-
ters(HMS77C1000A),
ters(HMS77C1001A). A physical transfer of register
contents from the program counter to the stack or vice ver-
sa, and within the stack, occurs on call and return instruc-
tions. If more than two sequential call instructions are
executed, only the most recent two return address are
stored. If more than two sequential return instructions are
executed, the stack will be filled with the address previous-
ly stored in level 2. The stack cannot be read or written by
10-bit
save
regis-
jump instrunciton
PCL
PC
8
0
Instruction Word
subroutine call instruction
jump instruction
subroutine call Instruction
FIGURE 9-6 LOADING OF BRANCH INSTRUCTION -
HMS77C1001A
FIGURE 9-5 LOADING OF BRANCH INSTRUCTION -
HMS77C1000A
PCL
PC
8
7
0
Instruction Word
Reset to ‘0’
PCL
PC
8
0
Instruction Word
9
PA0
PCL
PC
8
7
0
Instruction Word
9
PA0
Reset to ‘0’
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