參數(shù)資料
型號(hào)： HMS77C1001A
廠商： Hynix Semiconductor Inc.
元件分類： 數(shù)學(xué)處理器
英文描述： 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 8位單晶片微控制器
文件頁數(shù)： 22/45頁
文件大小： 549K
代理商： HMS77C1001A
HMS77C1000A/HMS77C1001A
Oct. 2001 Ver. 2.0
19
9.3 Special Function Registers
This devices has seven special function register that are the
INDF register, the Program Counter(PC), the STATUS
register, File Select Register(FSR), 8-bit Timer(TMR0),
and I/O data register(RA, RB).
The Special Function Registers are registers used by the
CPU and peripheral functions to control the operation of
the device (Table 9-1).
TMR0, RA and RB are not in the G700 CPU. They are lo-
cated in each peripheral function blocks. All special func-
tion register are placed on data memory map. The INDF
register is not a physical register and this register is used
for indirect addressing mode...
Legend : Shaded boxes = unimplemented or unused, - = unimplemented, read as ‘0’
x = unknown, u = unchanged, q = see the tables in Section 17 for possible values.
9.3.1 INDF Register
The INDF register is not physically implemented register,
used for indirect addressing mode. If the INDF register
are accessed, CPU goes to indirect addressing mode. Then
CPU accesses the Data memory which address is the con-
tents of FSR.
If the INDF register are accessed in indirect addressing
mode(I.e., FSR=00H), 00H will be loaded into data bus.
This time, note the arithmetic status bits of STATUS reg-
ister may be affected.
The FSR<4:0> bits are used to select data memory ad-
dresses 00
H
to 1F
H
.
HMS77C1000A and HMS77C1001A do not use banking.
FSR<7:5> are unimplemented and read as '1's.
Name
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Power-On
Reset
RESET and
WDT Reset
TRIS
N/A
I/O control registers (TRISA, TRISB)
1111 1111
1111 1111
OPTION
N/A
Contains control bits to configure Timer0, Timer0/WDT
prescaler and PFD
0011 1111
0011 1111
INDF
00
H
Uses contents of FSR to address data memory (not a
physical register)
xxxx xxxx
uuuu uuuu
TMR0
01
H
8-bit real-time clock/counter
xxxx xxxx
uuuu uuuu
PCL
02
H
Low order 8bits of PC
1111 1111
1111 1111
STATUS
03
H
-
-
PA0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
FSR
04
H
Indirect data memory address pointer
1xxx xxxx
1uuu uuuu
RA
05
H
-
-
-
-
RA3
RA2
RA1
RA0
---- xxxx
---- uuuu
RB
06
H
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
TABLE 9-1 SPECIAL FUNCTION REGISTER SUMMARY
FIGURE 9-4 DIRECT/INDIRECT ADDRESSING
4
0
4
0
(opcode)
(FSR)
location
select
location
select
Data
Memory
00
H
0F
H
10
H
1F
H
Direct Addressing
Indirect Addressing
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