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參數(shù)資料
| 型號(hào)： | HMS77C1001A |
| 廠商： | Hynix Semiconductor Inc. |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 36/45頁 |
| 文件大?。?/td> | 549K |
| 代理商： | HMS77C1001A |
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HMS77C1000A/HMS77C1001A
Oct. 2001 Ver. 2.0
33
14. RESET
HMS77C100XA devices may be reset in one of the follow-
ing ways:
- Power-On Reset (POR)
- Power-Fail detect reset (PFDR)
- RESET (normal operation)
- RESET wake-up reset (from SLEEP)
- WDT reset (normal operation)
- WDT wake-up reset (from SLEEP)
Each one of these reset conditions causes the program
counter to branch to reset vector address. (HMS77C1000A
is 1FF
H
and HMS77C1001A is 3FF
H
).
Table 14-1 shows these reset conditions for the PCL and
STATUS registers.
Some registers are not affected in any reset condition.
Their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset state”
on Power-On Reset (POR), PFDR, RESET or WDT reset.
A RESET or WDT wake-up from SLEEP also results in a
device reset, and not a continuation of operation before
SLEEP.
The TO and PD bits (STATUS <4:3>) are set or cleared
depending on the different reset conditions. These bits may
be used to determine the nature of the reset.
Table 14-2 lists a full description of reset states of all reg-
isters. Figure 14-1 shows a simplified block diagram of the
on-chip reset circuit.
Condition
PCL
Addr: 02
H
STATUS
Addr: 03
H
Power-On Reset
1111 1111
0001 1xxx
RESET reset or PFD
reset (normal operation)
1111 1111
000u uuuu
1
1. TO and PD bits retain their last value until one of the other
reset conditions occur.
2. The CLRWDT instruction will set the TO and PD bits.
Legend : x = unknown, u = unchanged.
RESET wake-up or PFD
reset (from SLEEP)
1111 1111
0001 0uuu
WDT reset (normal
operation)
1111 1111
0000 uuuu
2
WDT wake-up (from
SLEEP)
1111 1111
0000 0uuu
TABLE 14-1 RESET CONDITIONS FOR SPECIAL
REGISTERS
Register
Address
Power-On
Reset
Wake-up
Reset
RESET, PFDR,
WDT Reset
W
N/A
xxxx xxxx
uuuu uuuu
uuuu uuuu
TRIS
N/A
1111 1111
1111 1111
1111 1111
OPTION
N/A
0011 1111
0011 1111
0011 1111
INDF
00
H
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR0
01
H
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
1
02
H
1111 1111
1111 1111
1111 1111
STATUS
1
03
H
0001 1xxx
100q quuu
000q quuu
FSR
04
H
1xxx xxxx
1uuu uuuu
1uuu uuuu
PORTA
05
H
---- xxxx
---- uuuu
---- uuuu
PORTB
06
H
xxxx xxxx
uuuu uuuu
uuuu uuuu
General Purpose Register Files
07-1F
H
xxxx xxxx
uuuu uuuu
uuuu uuuu
TABLE 14-2 RESET CONDITIONS FOR ALL REGISTERS
1. See Table 14-1 for reset value for specific conditions.
Legend : - = unimplemented, read as ‘0’, x = unknown, u = unchanged.
q = see the tables in Section 17 for possible values.
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