23
SCL
18
I
I
2
C Interface Clock Input. The circuit for this pin should include a 4-6k
pull-up resistor con-
nected to VAA.
SA
19
I
I
2
C Interface Address Select Input.
SDA
20
I/O
I
2
C Interface Data Input/Output. The circuit for this pin should include a 4-6k
pull-up resis-
tor connected to VAA.
RESET
25
I
Reset Control Input. A logical zero for a minimum of four CLK cycles resets the device. RE-
SET must be a logical one for normal operation.
Y
3
O
Luminance Analog Current Output. This output contains luminance video, sync, blanking,
and information. It is capable of driving a 37.5
load. If not used, it should be connected to
GND and the DAC should be powered down.
C
7
O
Chrominance Analog Current Output. This output contains chrominance video, and blanking
information. It is capable of driving a 37.5
load. If not used, it should be connected to GND
and the DAC should be powered down.
NTSC/PAL
11
O
Composite Video Analog Current Output. This output contains composite video, sync, blank-
ing, and information. It is capable of driving a 37.5
load. If not used, it should be connected
to GND and the DAC should be powered down.
VREF
61
I/O
Voltage Reference. An optional external 1.235V reference may be used to drive this pin. If
left floating, the internal voltage reference is used.
FS_ADJUST
62
Full Scale Adjust Control. A resistor (RSET) connected between this pin and GND sets the
full-scale output current of each of the DACs.
COMP 1
64
Compensation Pin. A 0.1
μ
F ceramic chip capacitor should be connected between this pin
and VAA, as close to the device as possible.
COMP 2
63
Compensation Pin. A 0.1
μ
F ceramic chip capacitor should be connected between this pin
and VAA as close to the device as possible.
VAA
+5V Power. A 0.1
μ
F ceramic capacitor, in parallel with a 0.01
μ
F chip capacitor, should be
used between each group of VAA pins and GND. These should be as close to the device as
possible.
GND
Ground.
Pin Descriptions
(Continued)
PIN
NAME
PIN
NUMBER
INPUT/
OUTPUT
DESCRIPTION
HMP8190, HMP8191