參數(shù)資料
型號(hào)： HMP8190CN
廠商： HARRIS SEMICONDUCTOR
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： NTSC/PAL Video Encoder
中文描述： COLOR SIGNAL ENCODER, PQFP64
文件頁(yè)數(shù)： 21/32頁(yè)
文件大?。?/td> 227K
代理商： HMP8190CN
21
1
FIELD Detect
Select
This bit specifies whether an odd or even field is starting when the leading edge of HSYNC
occurs within the FIELD Detect Window. It is ignored unless HSYNC and VSYNC are config-
ured as inputs.
0 = odd field
1 = even field
0
B
0
Field Detect
Window Size High
This bit is cascaded with Field Detect Window Size Low to form a 9-bit Field Detect Window Size
value. This bit is ignored unless HSYNC and VSYNC are configured as inputs.
0
B
TABLE 39. FIELD CONTROL REGISTER 2
SUB ADDRESS = 27
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
TABLE 40. PHASE INCREMENT REGISTER 0
SUB ADDRESS = 6B
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-0
PHINC 0
(LSB)
The 8-bit registers PHINC 0–3 are cascaded together to form a 32-bit PHINC value. The
PHINC value is the phase increment value of the color subcarrier generation NCO. When the
BT.656 ancillary data is selected as the PHINC source, the PHINC registers may be read to
determine the last PHINC value loaded via the selected interface.
00
H
TABLE 41. PHASE INCREMENT REGISTER 1
SUB ADDRESS = 6C
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-0
PHINC 1
The 8-bit registers PHINC 0–3 are cascaded together to form a 32-bit PHINC value. The
PHINC value is the phase increment value of the color subcarrier generation NCO. When the
BT.656 ancillary data is selected as the PHINC source, the PHINC registers may be read to
determine the last PHINC value loaded via the selected interface.
00
H
TABLE 42. PHASE INCREMENT REGISTER 2
SUB ADDRESS = 6D
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-0
PHINC 2
The 8-bit registers PHINC 0–3 are cascaded together to form a 32-bit PHINC value. The
PHINC value is the phase increment value of the color subcarrier generation NCO. When the
BT.656 ancillary data is selected as the PHINC source, the PHINC registers may be read to
determine the last PHINC value loaded via the selected interface.
00
H
TABLE 43. PHASE INCREMENT REGISTER 1
SUB ADDRESS = 6E
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-0
PHINC 3
(MSB)
The 8-bit registers PHINC 0–3 are cascaded together to form a 32-bit PHINC value. The
PHINC value is the phase increment value of the color subcarrier generation NCO. When the
BT.656 ancillary data is selected as the PHINC source, the PHINC registers may be read to
determine the last PHINC value loaded via the selected interface.
00
H
HMP8190, HMP8191
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