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參數(shù)資料
| 型號： | HMP8117CN |
| 廠商： | INTERSIL CORP |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | NTSC/PAL Video Decoder |
| 中文描述： | COLOR SIGNAL DECODER, PDSO80 |
| 封裝： | PLASTIC, MS-022GB-1, MQFP-80 |
| 文件頁數(shù)： | 35/45頁 |
| 文件大?。?/td> | 269K |
| 代理商： | HMP8117CN |
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TABLE 52. WSS_CRC_EVEN DATA REGISTER
SUB ADDRESS = 29
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-6
Reserved
00
B
5-0
Even Field
WSS CRC Data
If even field WSS is enabled and present during NTSC operation, this register is loaded with the
six bitsof CRC information online 283.It isalways a “000000”during PAL operation. Datawritten
to this register is ignored.
000000
B
TABLE 53. START H_BLANK LSB REGISTER
SUB ADDRESS = 30
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Assert BLANK
Output Signal
This 8-bit register is cascaded with Start H_BLANK High Register to form a 10-bit start horizontal
blank REGISTER. It specifies the horizontal count (in 1x clock cycles) at which to assert BLANK
each scan line. Bit 0 is always a “0”, so the start of horizontal blanking may only be done with two
pixel resolution. The leading edge of HSYNC is count 000
H
.
4A
H
TABLE 54. START H_BLANK MSB REGISTER
SUB ADDRESS = 31
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
15-10
Reserved
000000
B
9-8
Assert BLANK
Output Signal
This 2-bit register is cascaded with Start H_BLANK Low Register to form a 10-bit start horizontal
blank register. It specifies the horizontal count (in 1x clock cycles) at which to assertBLANK each
scan line. The leading edge of HSYNC is count 000
H
.
11
B
TABLE 55. END H_BLANK REGISTER
SUB ADDRESS = 32
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Negate BLANK
Output Signal
This 8-bit register specifies the horizontal count (in 1x clock cycles) to negate BLANK each scan
line. For proper operation, bit 0 must always be set to “0”; therefore, the end of horizontal
blanking may only set with two pixel resolution. If bit 0 is set to “1”, the chroma/luma output data
may be swapped. The leading edge of HSYNC is count 000
H
.
7A
H
TABLE 56. START V_BLANK LSB REGISTER
SUB ADDRESS = 33
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Assert BLANK
Output Signal
This 8-bit register is cascaded with Start V_BLANK High Register to form a 9-bit start vertical
blank register. It specifies the line number to assert BLANK each field.
For NTSC operation, it occurs on line (n + 5) on odd fields and line (n + 268) on even fields. For
PAL operation, it occurs on line (n + 5) on odd fields and line (n + 318) on even fields.
02
H
TABLE 57. START V_BLANK MSB REGISTER
SUB ADDRESS = 34
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
15-9
Reserved
0000000
B
8
Assert BLANK
Output Signal
This 1-bit register is cascaded with Start V_BLANK Low Register to form a 9-bit start vertical
blank register.
1
B
HMP8117
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HMP8117CN96 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8117CNZ | 功能描述:編碼器、解碼器、復用器和解復用器 W/ANNEAL 80PQFP 0+70 DECODER W/MA RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| HMP8154 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Encoders |
| HMP8154_05 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Encoders |
| HMP8154CN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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