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參數(shù)資料
| 型號： | HMP8117CN |
| 廠商： | INTERSIL CORP |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | NTSC/PAL Video Decoder |
| 中文描述： | COLOR SIGNAL DECODER, PDSO80 |
| 封裝： | PLASTIC, MS-022GB-1, MQFP-80 |
| 文件頁數(shù)： | 10/45頁 |
| 文件大小： | 269K |
| 代理商： | HMP8117CN |
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10
BLANK and DVALID Timing
DVALID is asserted when P15-P0 contain valid data. The
behavior of the DVALID output is determined by bit 4
(DVLD_LTC) and bit 5 (DLVD_DCYC) of the GENLOCK
CONTROL register 04
H
for each video output mode.
The BLANK output pin is used to distinguish the blanking
interval period from active video data. The blanking intervals
are programmable in both horizontal and vertical
dimensions. Reference Figure 7 for active video timing and
use Table 3 for typical blanking programming values.
During active scan lines, BLANK is asserted when the
horizontal pixel count matches the value in the START
H_BLANK register 31
H
/30
H
. The pixel counter is 000
H
at the
leading edge of the sync tip after a fixed pipeline delay. Since
blanking normally occurs on the front porch, (prior to count
000H) the START H_BLANK count must be programmed
with a large value from the previous line. Refer to the Last
Pixel Count from Table 3. BLANK is negated when the
horizontal pixel count matches the value in the END
H_BLANK register 32
H
. Note that horizontally, BLANK is
programmable with two pixel resolution.
START V_BLANK register 34
H
/33
H
and END V_BLANK
register 35
H
determine which scan lines are blanked for each
field. During inactive scan lines, BLANK is asserted during the
entire scan line. Half-line blanking of the output video cannot
be done.
FIGURE 4. NTSC(M) AND PAL(M) EVEN FIELD TIMING
VIDEO
INPUT
VSYNC
FIELD
‘ODD’ FIELD
‘EVEN’ FIELD
HSYNC
261
PAL(M) LINE#
262
263
264
265
266
267
268
269
270
260
259
264
NTSC(M) LINE#
265
266
267
268
269
270
271
272
273
263
262
VIDEO
INPUT
VSYNC
FIELD
‘EVEN’ FIELD
FIGURE 5. PAL(B, D, G, H, I, N, N
C
) ODD FIELD TIMING
‘ODD’ FIELD
HSYNC
623
LINE #
624
625
1
2
3
4
5
6
7
622
621
FIGURE 6. PAL(B, D, G, H, I, N, N
C
) EVEN FIELD TIMING
VIDEO
INPUT
VSYNC
FIELD
‘ODD’ FIELD
‘EVEN’ FIELD
HSYNC
311
LINE #
312
313
314
315
316
317
318
319
320
310
309
HMP8117
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HMP8117CN96 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8117CNZ | 功能描述:編碼器、解碼器、復用器和解復用器 W/ANNEAL 80PQFP 0+70 DECODER W/MA RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| HMP8154 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Encoders |
| HMP8154_05 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Encoders |
| HMP8154CN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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