34
TABLE 37. SHARPNESS REGISTER
SUB ADDRESS = 1E
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-6
Reserved
00
B
5-0
Sharpness
Adjust
These bits control the amount of gain control of high frequency luminance signals (either
2.6MHz or Fsc). They may have a value of +12dB (“11 1111”) to -12dB (“00 0100”). A val-
ue of 0dB (“01 0000”) has no effect on the data. This register is ignored if the sharpness
mode selection is “disable sharpness control” or “reserved”.
010000
B
TABLE 38. HOST CONTROL REGISTER
SUB ADDRESS = 1F
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Software Reset
When this bit is set to 1, the entire device except the I
2
C bus is reset to a known state
exactly like the RESET input going active. The software reset will initialize all register bits
to their reset state. Once set this bit is self clearing. This bit is cleared on power-up by the
external RESET pin.
0
B
6
Power Down
When this bit is set to a 1, the entire device is shut down except the I
2
C bus by gating off
the clock. For normal decoding operations this bit should be set to a 0.
0
B
5
Closed Caption
Odd Field
Read Status
This bit is read-only. Data written to this bit is ignored. The bit is cleared when the caption
data has been read out via the I
2
C interface or as BT.656 ancillary data.
0 = No new caption data
1 = Caption_ODD_A and Caption_ODD_B data registers contain new data.
0
B
4
Closed Caption
Even Field
Read Status
This bit is read-only. Data written to this bit is ignored. The bit is cleared when the caption
data has been read out via the I
2
C interface or as BT.656 ancillary data.
0 = No new caption data
1 = Caption_EVEN_A and Caption_EVEN_B data registers contain new data.
0
B
3
WSS
Odd Field
Read Status
This bit is read-only. Data written to this bit is ignored. The bit is cleared when the WSS
data has been read out via the I
2
C interface or as BT.656 ancillary data.
0 = No new WSS data
1 = WSS_ODD_A and WSS_ODD_B data registers contain new data.
0
B
2
WSS
Even Field
Read Status
This bit is read-only. Data written to this bit is ignored. The bit is cleared when the WSS
data has been read out via the I
2
C interface or as BT.656 ancillary data.
0 = No new WSS data
1 = WSS_EVEN_A and WSS_EVEN_B data registers contain new data.
0
B
1-0
Reserved
00
B
TABLE 39. CLOSED CAPTION_ODD_A DATA REGISTER
SUB ADDRESS = 20
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Odd Field
Caption Data
If odd field captioning is enabled and present, this register is loaded with the first eight bits
of caption data on line 18, 21, or 22. Bit 0 corresponds to the first bit of caption information.
Data written to this register is ignored.
80
H
TABLE 40. CLOSED CAPTION_ODD_B DATA REGISTER
SUB ADDRESS = 21
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
15-8
Odd Field
Caption Data
If odd field captioning is enabled and present, this register is loaded with the second eight
bits of caption data on line 18, 21, or 22. Data written to this register is ignored.
80
H
HMP8116