- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385388 > HMP8116 (Intersil Corporation) NTSC/PAL Video Decoder PDF資料下載
參數(shù)資料
| 型號： | HMP8116 |
| 廠商： | Intersil Corporation |
| 英文描述： | NTSC/PAL Video Decoder |
| 中文描述： | NTSC / PAL視頻解碼器 |
| 文件頁數(shù)： | 26/43頁 |
| 文件大小： | 182K |
| 代理商： | HMP8116 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁
26
TABLE 14. GENLOCK CONTROL REGISTER
SUB ADDRESS = 04
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Aspect Ratio
Mode
0 = Rectangular (BT.601) pixels
1 = Square pixels
0
B
6
Freeze Output
Timing Enable
Setting this bit to a “1” freezes the output timing at the end of the field. Resetting this bit
to a “0” resumes normal operation at the start of the next field.
0 = Normal operation
1 = Freeze output timing
0
B
5
DVALID Duty Cycle
Control
(DVLD_DCYC)
This bit is ignored during the 8-bit YCbCr and BT.656 output modes.
During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as:
0 = DVALID has 50/50 duty cycle at the pixel output datarate
1 = DVALID goes active based on linelock. This will cause DVALID to not have a 50/50
duty cycle. This bit is intended to be used in maintaining backward compatibilty with the
HMP8112A DVALID output timing.
0
B
4
DVALID Line Timing
Control
(DVLD_LTC)
During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as:
0 = DVALID present only during active video time on active scan lines
1 = DVALID present the entire scan line time on all scan lines
During the 8-bit YCbCr and BT.656 output modes, this bit defines the DVALID output sig-
nal as:
0 = Normal timing
1 = DVALID signal ANDed with CLK2
0
B
3
Missing HSYNC
Detect Select
Thisbitspecifies thenumberof missinghorizontalsyncpulses beforethedevicegoes into
the horizontal lock acquisition mode. In mode “0”, the default value of the HPLL Adjust
register should be used. In mode “1”, the typical values the HPLL Adjust register should
be 10
H
to 20
H
.
0 = 12 pulses
1 = 1 pulse
0
B
2
Missing VSYNC
Detect Select
This bit specifies the number of missing vertical sync pulses before the device goes into
the vertical lock acquisition mode.
0 = 3 pulses
1 = 1 pulse
0
B
1-0
CLK2 Frequency
This bit indicates the frequency of the CLK2 input clock.
00 = 24.54MHz
01 = 27.0MHz
10 = 29.5MHz
11 = Reserved
01
B
HMP8116
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HMP8116CN | NTSC/PAL Video Decoder |
| HMP8117 | NTSC/PAL Video Decoder |
| HMP8117CN | NTSC/PAL Video Decoder |
| HMP8154 | NTSC/PAL Encoders |
| HMP8154CN | NTSC/PAL Encoders |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HMP8116CN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Decoder |
| HMP8117 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Decoder |
| HMP8117_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Decoder |
| HMP8117CN | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 80PQFP,0+70C NTSC/PAL VIDEO DECODER W/MA RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| HMP8117CN96 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。