8 GHz fractional syntHesizer For price" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� HMC703LP4E
寤犲晢锛� Hittite Microwave Corporation
鏂囦欢闋佹暩(sh霉)锛� 41/58闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FRACT-N PLL W/SWEEPR 24QFN
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
椤炲瀷锛� 鏁存暩(sh霉) N/灏忔暩(sh霉) N 鍒嗛牷
PLL锛� 鏄�
杓稿叆锛� CMOS
杓稿嚭锛� CMOS
闆昏矾鏁�(sh霉)锛� 1
姣旂巼 - 杓稿叆:杓稿嚭锛� 1:1
宸垎 - 杓稿叆:杓稿嚭锛� 鏄�/鐒�
闋荤巼 - 鏈€澶э細 8GHz
闄ゆ硶鍣�/涔樻硶鍣細 鏄�/鐒�
闆绘簮闆诲锛� 3.3V锛�5V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 24-VQFN 瑁搁湶鐒婄洡
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 24-QFN 瑁搁湶鐒婄洡锛�4x4锛�
鍖呰锛� 妯�(bi膩o)婧�(zh菙n)鍖呰
鍏跺畠鍚嶇ū锛� 1127-1065-6
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HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 978-250-3373 fax Order On-line at www.hittite.com
Application Support: pll@hittite.com
table 16. reg 03h frequency register - integer Part
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
[15:0]
R/W
intg
16
25d
The (base) integer portion of the prescaler divide ratio. In any of
the fractional modes of operation, this value is double buffered, and
does not take effect until a 鈥楾rigger鈥� event. see 鈥極peration Modes鈥�
for more information. In integer mode, this value can range from
16 to 65535. In fractional mode it should be restricted between 20
and 65531.
table 17. reg 04h frequency register - fractional Part
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
[23:0]
R/W
frac
24
0
VCO Divider Fractional part (24 bit unsigned) see Fractional
Frequency Tuning
NFRAC = Reg 04h/224
Used in Fractional Modes only
min 0d
max 2^24-1 = FFFFFFh = 16,777,215d
table 18. reg 05h seed
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
[23:0]
R/W
sEED
24
654321h
The initial starting point for the fractional modulator at the 鈥淭rigger鈥�
position. This value effects the phase of the output, and can effect
some types of spurious content. During sweeps, the modulator can
optionally be reloaded with this value at the start of each ramp.
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
HMC703LP4ETR 鍒堕€犲晢:Hittite Microwave Corp 鍔熻兘鎻忚堪:IC FRACT-N PLL W/SWEEPR 24QFN 鍒堕€犲晢:Hittite Microwave Corp 鍔熻兘鎻忚堪:8 GHz Fractional-N PLL with Sweeper
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HMC7043LP7FETR 鍔熻兘鎻忚堪:IC FRACT-N PLL W/SWEEPR 48LFCSP 鍒堕€犲晢:analog devices inc. 绯诲垪:- 鍖呰:鍓垏甯讹紙CT锛� 闆朵欢鐙€鎱�(t脿i):鍦ㄥ敭 椤炲瀷:鏅�(sh铆)閻樼珐娌栧櫒 PLL:鏄� 杓稿叆:鏅�(sh铆)閻� 杓稿嚭:CMOS锛孡VDS锛孡VPECL 闆昏矾鏁�(sh霉):1 姣旂巼 - 杓稿叆:杓稿嚭:1锛�14 宸垎 - 杓稿叆:杓稿嚭:鏄�/鏄� 闋荤巼 - 鏈€澶у€�:3.2GHz 鍒嗛牷鍣�/鍊嶉牷鍣�:鏄�/鐒� 闆诲 - 闆绘簮:3.135 V ~ 3.465 V 宸ヤ綔婧害:-40掳C ~ 85掳C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:48-VFQFN 瑁搁湶鐒婄洡锛孋SP 渚涙噳(y墨ng)鍟嗗櫒浠跺皝瑁�:48-LFCSP锛�7x7锛� 妯�(bi膩o)婧�(zh菙n)鍖呰:1
HMC7044LP10BETR 鍔熻兘鎻忚堪:IC JITTER ATTENUATOR 68LFCSP 鍒堕€犲晢:analog devices inc. 绯诲垪:- 鍖呰:鍓垏甯讹紙CT锛� 闆朵欢鐙€鎱�(t脿i):鍦ㄥ敭 椤炲瀷:婕傜Щ琛版笡鍣� PLL:鏄� 杓稿叆:CML锛孋MOS锛孡VDS锛孡VPECL 杓稿嚭:CML锛孡VDS锛孡VPECL 闆昏矾鏁�(sh霉):1 姣旂巼 - 杓稿叆:杓稿嚭:4:14 宸垎 - 杓稿叆:杓稿嚭:鏄�/鏄� 闋荤巼 - 鏈€澶у€�:3.2GHz 鍒嗛牷鍣�/鍊嶉牷鍣�:鏄�/鐒� 闆诲 - 闆绘簮:3.135 V ~ 3.465 V 宸ヤ綔婧害:-40掳C ~ 85掳C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:68-VFQFN 瑁搁湶鐒婄洡锛孋SP 渚涙噳(y墨ng)鍟嗗櫒浠跺皝瑁�:68-LFCSP-VQ锛�10x10锛� 妯�(bi膩o)婧�(zh菙n)鍖呰:1
HMC704LP4E 鍔熻兘鎻忚堪:IC FRACT-N PLL 16BIT 24QFN RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏅�(sh铆)閻�/瑷�(j矛)鏅�(sh铆) - 鏅�(sh铆)閻樼櫦(f膩)鐢熷櫒锛孭LL锛岄牷鐜囧悎鎴愬櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:2,000 绯诲垪:- 椤炲瀷:PLL 闋荤巼鍚堟垚鍣� PLL:鏄� 杓稿叆:鏅堕珨 杓稿嚭:鏅�(sh铆)閻� 闆昏矾鏁�(sh霉):1 姣旂巼 - 杓稿叆:杓稿嚭:1:1 宸垎 - 杓稿叆:杓稿嚭:鐒�/鐒� 闋荤巼 - 鏈€澶�:1GHz 闄ゆ硶鍣�/涔樻硶鍣�:鏄�/鐒� 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:-20°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:16-LSSOP锛�0.175"锛�4.40mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:16-SSOP 鍖呰:甯跺嵎 (TR) 鍏跺畠鍚嶇ū:NJW1504V-TE1-NDNJW1504V-TE1TR