8 GHz fractional syntHesizer For price" />
參數(shù)資料
型號(hào)： HMC703LP4E
廠商： Hittite Microwave Corporation
文件頁數(shù)： 15/58頁
文件大?。?/td> 0K
描述： IC FRACT-N PLL W/SWEEPR 24QFN
標(biāo)準(zhǔn)包裝： 1
類型： 整數(shù) N/小數(shù) N 分頻
PLL： 是
輸入： CMOS
輸出： CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/無
頻率 - 最大： 8GHz
除法器/乘法器： 是/無
電源電壓： 3.3V，5V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-VQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 24-QFN 裸露焊盤（4x4）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 1127-1065-6
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HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 978-250-3373 fax Order On-line at www.hittite.com
Application Support: pll@hittite.com
As an example, suppose we want to tune a VCO to 7910 MHz. since the input frequency is > 4 GHz, the
RF divide-by-2 must be engaged, so k=2:
fvco
7,910 MHz
k
2
fps
3,955 MHz
fxtal
= 50 MHz
R
= 1
fpd
= 50 MHz
Nint
= 79
Nfrac
= 0.1
= round(0.1 x 224) = round(1677721.6) = 1677722
fps =
(79 +
) = 3955 MHz + 1.2 Hz error
1677722
224
50e6
1
(eQ 7)
fvco = 2 (3955 +1.2 Hz) = 7910 MHz + 2.4 Hz error
(eQ 8)
In this example the output frequency of 7910 MHz is achieved by programming the 16-bit binary value of 79d = 4Fh =
0000 0000 0100 1111 into intg_reg in Reg 03h, and the 24-bit binary value of 1677722d = 19999Ah = 0001 1001 1001
1001 1001 1010 into frac_reg in Reg 04h. The 2.4 Hz quantization error can be eliminated using the exact frequency
mode if required.
exact frequency Mode
The absolute frequency precision of a fractional PLL is normally limited by the number of bits in the fractional modulator.
For example a 24 bit fractional modulator has frequency resolution set by the phase detector (PD ) comparison rate
divided by 224. In the case of a 50 MHz PD rate, this would be approximately 2.98 Hz, or 0.0596 ppm.
In some applications it is necessary to have exact frequency steps, and even an error of 3 Hz cannot be tolerated. In
some fractional synthesizers it is necessary to shorten the length of the accumulator (the denominator or the modulus)
to accommodate the exact period of the step size. The shortened accumulator often leads to very high spurious levels
at multiples of the channel spacing, fstep = fPD/Modulus. For example 200 kHz channel steps with a 10 MHz PD rate
requires a modulus of just 50. The Hittite method achieves the exact frequency step size while using the full 24 bit
modulus, thus achieving exact frequency steps with very low spurious and a high comparison rate, which maintains
excellent phase noise.
Fractional PLLs are able to generate exact frequencies (with zero frequency error) if N can be exactly represented in
binary (eg. N = 50.0,50.5,50.25,50.75 etc.). Unfortunately, some common frequencies cannot be exactly represented.
For example, Nfrac = 0.1 = 1/10 must be approximated as round((0.1 x 224)/ 224 ) ≈ 0.100000024. At fPD = 50 MHz this
translates to 1.2 Hz error. HMC703LP4E exact frequency mode addresses this issue, and can eliminate quantization
error by programming the Nchannels (Reg 0Dh) to 10 (in this example). More generally, this feature can be used whenever
the prescaler frequency, fps, can be exactly represented on a step plan where there are an integer number (Nchannels)
of frequency steps across integer-N boundaries. Assuming the RF divide by 2 is disabled so that fps=fvco, this holds
when the VCO frequency, fvco satisfies (EQ 9), shown graphically in Figure 30.
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