- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗1996 > HMC703LP4E (Hittite Microwave Corporation)IC FRACT-N PLL W/SWEEPR 24QFN PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | HMC703LP4E |
| 寤犲晢锛� | Hittite Microwave Corporation |
| 鏂囦欢闋佹暩(sh霉)锛� | 28/58闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FRACT-N PLL W/SWEEPR 24QFN |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 椤炲瀷锛� | 鏁存暩(sh霉) N/灏忔暩(sh霉) N 鍒嗛牷 |
| PLL锛� | 鏄� |
| 杓稿叆锛� | CMOS |
| 杓稿嚭锛� | CMOS |
| 闆昏矾鏁�(sh霉)锛� | 1 |
| 姣旂巼 - 杓稿叆:杓稿嚭锛� | 1:1 |
| 宸垎 - 杓稿叆:杓稿嚭锛� | 鏄�/鐒� |
| 闋荤巼 - 鏈€澶э細 | 8GHz |
| 闄ゆ硶鍣�/涔樻硶鍣細 | 鏄�/鐒� |
| 闆绘簮闆诲锛� | 3.3V锛�5V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 24-VQFN 瑁搁湶鐒婄洡 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 24-QFN 瑁搁湶鐒婄洡锛�4x4锛� |
| 鍖呰锛� | 妯�(bi膩o)婧�(zh菙n)鍖呰 |
| 鍏跺畠鍚嶇ū锛� | 1127-1065-6 |
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HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 978-250-3373 fax Order On-line at www.hittite.com
Application Support: pll@hittite.com
PD Force Mid Reg 0Bh[9] will disable the charge pump current sources and place a voltage source on the loop filter at
approximately VPPCP/2. If a passive filter is used this will set the VCO to the mid-voltage tuning point which can be
useful for testing of the VCO.
lock Detect
Each PD (Phase Detector) cycle, the HMC703LP4E measures phase error at the PD. The measured phase error must
be:
< ~220 degrees if 40 MHz <= fPD <= 120 MHz, and
< ~14 ns if fpd < 40 MHz,
for a number of consecutive cycles (number of cycles is programmable in Reg 07h[2:0]), in order for HMC703LP4E to
declare a lock. A single phase error outside of these criteria disqualifies lock, and the lock counter (maximum value of
lock counter = Reg 07h[2:0]) is restarted.
Note that in some cases, the PLL may be locked with a phase error that exceeds 180 degrees, or 12 ns, whichever is
smaller. This can occur if the offset current is inappropriately programmed too high. It is not recommended to operate
in this condition because it leads to degraded phase noise performance. In such a case the lock detect circuit would
not declare a locked condition, even though the PLL is locked.
The HMC703LP4E lock-detect functionality is self-calibrating relative to the reference frequency. Typically the
lock-detect training is only required once on power-up, or each time the reference frequency or the R divider value
(Reg 02h) is changed.
To train the lock-detect circuitry of the HMC703LP4E on power-up, set:
set Reg 07h [11] = 1 to enable lock-detect counters
set Reg 07h [14] = 1 to enable the lock-detect timer
set Reg 07h [20] = 1 to train the lock-detect timer
These bits can all be written simultaneously.
On any change of the PD frequency (via either the external reference frequency, or the R divider setting (Reg 02h)),
the lock-detect circuit should be retrained by toggling Reg 07h [20] Off and then back On.
The lock-detect indication can be read from the sPI via Reg 12h[1], or can be exported on the LD_sDO pin via the
GPO mux(Reg 0Fh[4:0]). see LD_sDO pin description for more information.
cycle slip Prevention (csP)
When changing frequency and the VCO is not yet locked to the reference, the instantaneous frequencies of the two PD
inputs are different, and the phase difference of the two inputs at the PD varies rapidly over a range much greater than
+/-2蟺 radians. since the gain of the PD varies linearly with phase up to +/-2蟺, the gain of a conventional PD will cycle
from high gain, when the phase difference approaches a multiple of 2蟺, to low gain, when the phase difference is
slightly larger than 0 radians. The output current from the charge pump will cycle from maximum to minimum even
though the VCO has not yet reached its final frequency.
The charge on the loop filter small cap may actually discharge slightly during the low gain portion of the cycle. This can
make the VCO frequency actually reverse temporarily during locking. This phenomenon is known as cycle slipping.
Cycle slipping causes the pull-in rate during the locking phase to vary cyclically. Cycle slipping increases the time to
lock to a value much greater than that predicted by normal small signal Laplace analysis.
The HMC703LP4E mitigates the effects of cycle-slips by increasing the charge-pump current when the phase error is
larger than ~220 degrees or ~14 ns (whichever is less as measured by the lock-detect circuit). The circuit is normally
most effective for PD frequencies <= 50 MHz.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| HMC704LP4E | IC FRACT-N PLL 16BIT 24QFN |
| HMC830LP6GE | IC FRACT-N PLL W/VCO 40QFN |
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| HMP8156ACNZ | IC VIDEO ENCODER NTSC/PAL 64MQFP |
| HSP45102SC-40Z | IC OSC NCO 40MHZ 28-SOIC |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| HMC703LP4ETR | 鍒堕€犲晢:Hittite Microwave Corp 鍔熻兘鎻忚堪:IC FRACT-N PLL W/SWEEPR 24QFN 鍒堕€犲晢:Hittite Microwave Corp 鍔熻兘鎻忚堪:8 GHz Fractional-N PLL with Sweeper |
| HMC7043LP7FE | 鍔熻兘鎻忚堪:IC FRACT-N PLL W/SWEEPR 48LFCSP 鍒堕€犲晢:analog devices inc. 绯诲垪:- 鍖呰:鍓垏甯讹紙CT锛� 闆朵欢鐙€鎱�(t脿i):鏂扮敘(ch菐n)鍝� 椤炲瀷:* PLL:鏄� 杓稿叆:鏅傞悩 杓稿嚭:CML锛孡VDS锛孡VPECL 闆昏矾鏁�(sh霉):1 姣旂巼 - 杓稿叆:杓稿嚭:1锛�14 宸垎 - 杓稿叆:杓稿嚭:鏄�/鏄� 闋荤巼 - 鏈€澶у€�:3.2GHz 鍒嗛牷鍣�/鍊嶉牷鍣�:鏄�/鐒� 闆诲 - 闆绘簮:3.135 V ~ 3.465 V 宸ヤ綔婧害:-40掳C ~ 85掳C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:48-VFQFN 瑁搁湶鐒婄洡锛孋SP 渚涙噳(y墨ng)鍟嗗櫒浠跺皝瑁�:48-LFCSP锛�7x7锛� 妯�(bi膩o)婧�(zh菙n)鍖呰:1 |
| HMC7043LP7FETR | 鍔熻兘鎻忚堪:IC FRACT-N PLL W/SWEEPR 48LFCSP 鍒堕€犲晢:analog devices inc. 绯诲垪:- 鍖呰:鍓垏甯讹紙CT锛� 闆朵欢鐙€鎱�(t脿i):鍦ㄥ敭 椤炲瀷:鏅傞悩绶╂矕鍣� PLL:鏄� 杓稿叆:鏅傞悩 杓稿嚭:CMOS锛孡VDS锛孡VPECL 闆昏矾鏁�(sh霉):1 姣旂巼 - 杓稿叆:杓稿嚭:1锛�14 宸垎 - 杓稿叆:杓稿嚭:鏄�/鏄� 闋荤巼 - 鏈€澶у€�:3.2GHz 鍒嗛牷鍣�/鍊嶉牷鍣�:鏄�/鐒� 闆诲 - 闆绘簮:3.135 V ~ 3.465 V 宸ヤ綔婧害:-40掳C ~ 85掳C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:48-VFQFN 瑁搁湶鐒婄洡锛孋SP 渚涙噳(y墨ng)鍟嗗櫒浠跺皝瑁�:48-LFCSP锛�7x7锛� 妯�(bi膩o)婧�(zh菙n)鍖呰:1 |
| HMC7044LP10BETR | 鍔熻兘鎻忚堪:IC JITTER ATTENUATOR 68LFCSP 鍒堕€犲晢:analog devices inc. 绯诲垪:- 鍖呰:鍓垏甯讹紙CT锛� 闆朵欢鐙€鎱�(t脿i):鍦ㄥ敭 椤炲瀷:婕傜Щ琛版笡鍣� PLL:鏄� 杓稿叆:CML锛孋MOS锛孡VDS锛孡VPECL 杓稿嚭:CML锛孡VDS锛孡VPECL 闆昏矾鏁�(sh霉):1 姣旂巼 - 杓稿叆:杓稿嚭:4:14 宸垎 - 杓稿叆:杓稿嚭:鏄�/鏄� 闋荤巼 - 鏈€澶у€�:3.2GHz 鍒嗛牷鍣�/鍊嶉牷鍣�:鏄�/鐒� 闆诲 - 闆绘簮:3.135 V ~ 3.465 V 宸ヤ綔婧害:-40掳C ~ 85掳C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:68-VFQFN 瑁搁湶鐒婄洡锛孋SP 渚涙噳(y墨ng)鍟嗗櫒浠跺皝瑁�:68-LFCSP-VQ锛�10x10锛� 妯�(bi膩o)婧�(zh菙n)鍖呰:1 |
| HMC704LP4E | 鍔熻兘鎻忚堪:IC FRACT-N PLL 16BIT 24QFN RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏅傞悩/瑷堟檪 - 鏅傞悩鐧�(f膩)鐢熷櫒锛孭LL锛岄牷鐜囧悎鎴愬櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:2,000 绯诲垪:- 椤炲瀷:PLL 闋荤巼鍚堟垚鍣� PLL:鏄� 杓稿叆:鏅堕珨 杓稿嚭:鏅傞悩 闆昏矾鏁�(sh霉):1 姣旂巼 - 杓稿叆:杓稿嚭:1:1 宸垎 - 杓稿叆:杓稿嚭:鐒�/鐒� 闋荤巼 - 鏈€澶�:1GHz 闄ゆ硶鍣�/涔樻硶鍣�:鏄�/鐒� 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:-20°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:16-LSSOP锛�0.175"锛�4.40mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:16-SSOP 鍖呰:甯跺嵎 (TR) 鍏跺畠鍚嶇ū:NJW1504V-TE1-NDNJW1504V-TE1TR |
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