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| 型號： | HMC703LP4E |
| 廠商： | Hittite Microwave Corporation |
| 文件頁數(shù)： | 10/58頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FRACT-N PLL W/SWEEPR 24QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 整數(shù) N/小數(shù) N 分頻 |
| PLL： | 是 |
| 輸入： | CMOS |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.3V，5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN 裸露焊盤（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | 1127-1065-6 |
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HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 978-250-3373 fax Order On-line at www.hittite.com
Application Support: pll@hittite.com
fractional operation
Unlike an integer synthesizer, spurious signals in a fractional synthesizer can occur due to the fact that the VCO
operates at frequencies unrelated to the PD frequency. Hence intermodulation of the VCO and the PD harmonics can
cause spurious sidebands. spurious emissions are largest when the VCO operates very close to an integer multiple of
the PD. When the VCO operates exactly at a harmonic of the PD then, no in-close mixing products are present.
Interference is always present at multiples of the PD frequency, fpd, and the VCO frequency, fvco. If the fractional mode
of operation is used, the difference, Δ, between the VCO frequency and the nearest harmonic of the reference, will
create what are referred to as integer boundary spurs. Depending upon the mode of operation of the synthesizer, higher
order, lower power spurs may also occur at multiples of integer fractions (sub-harmonics) of the PD frequency. That is,
fractional VCO frequencies which are near nfpd + fpdd/m, where n, d and m are all integers and d≤m (mathematicians
refer to d/m as a rational number). We will refer to fpdd/m as an integer fraction. The denominator, m, is the order of the
spurious product. Higher values of m produce smaller amplitude spurious at offsets of mΔ and usually when m>4 spurs
are very small or unmeasurable.
The worst case, in fractional mode, is when d=1, and the VCO frequency is offset from nfpd by less than the loop
bandwidth. This is the “in-band fractional boundary” case.
Figure 29. Fractional Spurious Example
Characterization of the levels and orders of these products is not unlike a mixer spur chart. Exact levels of the products
are dependent upon isolation of the various synthesizer parts. Hittite can offer guidance about expected levels of
spurious with our PLL and VCO application boards. Regulators with high power supply rejection ratios (PsRR) are
recommended, especially in noisy applications.
When operating in fractional mode, charge pump and phase detector linearity is of paramount importance. Any non-
linearity degrades phase noise and spurious performance. Phase detector linearity degrades when the phase error is
very small and is operating back and forth between reference lead and VCO lead. To mitigate these non-linearities in
fractional mode it is critical to operate the phase detector with some finite phase offset such that either the reference or
VCO always leads. To provide a finite phase error, extra current sources can be enabled which provide a constant DC
current path to VDD (VCO leads always) or ground (reference leads always). These current sources are called charge
pump offset and they are controlled via Reg 09h. The time offset at the phase detector should be ~2.5 ns + 4 Tps, where
Tps is the RF period at the fractional prescaler input in nanoseconds (ie. after the optional fixed divide by 2). The specific
level of charge pump offset current is determined by this time offset, the comparison frequency and the charge pump
current and can be calculated from:
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