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參數(shù)資料
| 型號： | HIP5061DS |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 12 A SWITCHING REGULATOR, 290 kHz SWITCHING FREQ-MAX, PZFM7 |
| 封裝： | STAGGERED GULL WING, TO-220, SIP-7 |
| 文件頁數(shù)： | 18/20頁 |
| 文件大小： | 158K |
| 代理商： | HIP5061DS |
7-70
HIP5061
390
μ
F, 50V, type 673D from United Chemicon). This change
would also greatly improve load transient response, pro-
vided that the loop compensation is appropriately adjusted.
Note that in the circuit of Figure 38, capacitor C12 does not
significantly affect output ripple, but is necessary to absorb
the energy stored in L2 during severe load transients. In the
event of a step change in load from 1.8A to 0A, C12 will limit
the output voltage overshoot to about 10V and protect the
drain of the DMOS transistor from overvoltage breakdown.
Input and V
DD
Filters
Since the boost converter is current fed, input filtering is eas-
ily achieved by the addition of a small capacitor C4. This
capacitor provides nearly 40dB of ripple current attenuation
for the input, reducing the AC ripple current flowing into the
converter to less than 200mA.
R5 and C3 have been chosen to provide good filtering of
high frequency pulse currents. R5 provides isolation
between the analog V
DD
pin and the high pulse current V
G
pin, and also provides a means to control the turn-on speed
of the DMOS transistor by limiting the peak current available
to the internal gate drive circuitry. Thus the output transition
time may be increased to prevent drain voltage undershoot.
Undershoot may result in activation of device parasitics and
improper circuit operation. For the two-layer board used for
this design, C3 could be reduced to 0.22
μ
F without affecting
circuit operation. C5 was added to provide low-frequency fil-
tering at the V
DD
pin. This reduces the tendency of the circuit
to oscillate off and on when the voltage at the V
DD
pin s in
the vicinity of the under voltage lockout threshold, typically
10V, and the output power is high (30W - 50W).
Shunt Regulator Resistor
Resistor RA has been chosen to be as large as possible to
reduce power dissipation at high line, while ensuring ade-
quate V
DD
voltage at low line. Note that the guaranteed
range of input voltage for proper operation of this circuit is
11.2V to 15.3VDC, based upon data sheet limits. However,
the circuit was found to perform well at room temperature for
V
I
= 10.7VDC to 17VDC. The maximum value for RA is
RA has been chosen as 20
, which results in a current into
the V
DD
clamp that is less than 105mA when the input volt-
age is at its maximum:
RMAX
,
----------------------------------------
10.5
–
21
=
=
IMAX
,
-------------------------------------------------
13.3
–
100mA
=
=
105mA
<
Snubber Network
A snubber network has been added to reduce the ringing at
the drain due to parasitic layout inductances. In particular,
under severe load transient conditions, this snubber is nec-
essary to protect the drain from voltage breakdown. A sec-
ond benefit of reducing the noise and ringing at the drain is
that it reduces the tendency of the HIP5061 to exhibit noise-
related instabilities at high peak DMOS transistor currents
(4A-6A). A value of 1000pF was chosen for C13, since this
is adequate to dampen the ringing associated with the
200pF drain capacitance of the DMOS transistor. R11 was
chosen as 7.5
to provide the best possible dampening
given the parasitic inductances that exist in the layout. Note
that this snubber may not be necessary if the layout of the
circuit were improved, or if the application did not push the
envelope of DMOS transistor current.
Other Power Supply Topologies
Figure 39 shows three other topologies besides the Boost that
may be implemented with the grounded source DMOS power
transistor used in the HIP5061. Other, more complex power
supply topologies such as the Quadratic are also possible to
implement with the HIP5061. One noteworthy feature of the
Quadratic topology as shown in Figure 41 is the wide input to
output voltage transfer ratio possible with reasonable duty
cycles. Duty cycles that are not near the Minimum DMOS tran-
sistor “ON” Time specification shown in the Data Sheet. This
permits easier control at the extremes of the transfer ratios.
Compensating the control loop can pose challenges because
of the wider changes in the transfer ratio and hence loop gain.
The SEPIC topology
[11,13]
does not have quite as wide input-
output voltage range with reasonably controlled duty cycles
as the Quadratic converter mentioned above, but it does
allow both voltage increase and decrease with the same cir-
cuit. This is particularly advantageous when a power supply
is being used in the stabilizing mode and isolation is not
required. For example, in an application where a regulated
24V output is required and the input voltage varies
±
20%
from a nominal 24V. The SEPIC supply can provide both the
Boost and Buck functions.
Another outstanding advantage of the SEPIC topology is its
fault isolation of the input and output voltage. All energy is
transferred via the coupling capacitor. Moreover if the clock
stops, voltage transfer stops. If the switching transistor shorts
there is no output. The Buck circuit will apply full input voltage
to the load with a shorted transistor. This is reason that the
SEPIC topology is referred to as the fail-safe Buck.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HIP5061DS WAF | 制造商:Harris Corporation 功能描述: |
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| HIP5062DW | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Power Control IC Single Chip Dual Switching Power Supply |
| HIP5062DY | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Power Control IC Single Chip Dual Switching Power Supply |
| HIP5063 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Power Control IC Single Chip Power Supply |
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