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參數(shù)資料
| 型號： | HIP5061DS |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 12 A SWITCHING REGULATOR, 290 kHz SWITCHING FREQ-MAX, PZFM7 |
| 封裝： | STAGGERED GULL WING, TO-220, SIP-7 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 158K |
| 代理商： | HIP5061DS |
7-67
HIP5061
esis of this comparator is intended to reduce oscillation
when the voltage at V
DD
is in the vicinity of 10V. Note, how-
ever, that when an external series resistor is used to feed the
shunt regulator, the voltage drop across this resistor (which
sharply decreases when the IC shuts down), effectively
reduces the hysteresis. To reduce the tendency for oscilla-
tion in the vicinity of the 10V threshold, the impedance of the
source that feeds the DC to DC converter input should be
minimized. The addition of a capacitor (1
μ
F-47
μ
F) at the
V
DD
terminal can also help to provide smooth turn-on or turn-
off of the converter if the input supply rises or falls gradually
through the V
DD
Comparator threshold.
Peak Controllable DMOS Transistor Current
Figure 34 shows the guaranteed minimum, peak controllable
DMOS transistor current versus duty cycle. This peak cur-
rent value is established by the current limit circuitry, which
effectively clamps the voltage at V
C
(the error voltage) to
perform current limiting. Since the sensed DMOS transistor
current is summed with a compensating current ramp that
begins its rise 1.5
μ
s after the initiation of a cycle, current lim-
iting will beginto occur at a peak DMOS transistor current
that varies with the operating duty cycle. The highest current
limit threshold occurs for D<0.375, where no ramp is added
to the sensed DMOS transistor current. At higher operating
duty ratios, the onset of current limit will occur at increasingly
lower currents, due to the effect of adding the compensating
ramp to the sensed current. Note that this curve represents
guaranteed minimum values. The guaranteed maximum val-
ues are considerable higher, although they are still limited to
levels that protect the IC.
FIGURE 34. PEAK DMOS TRANSISTOR DRAIN CURRENT vs
DUTY CYCLE
When the DMOS transistor first turns ON there may be sub-
stantial current spikes exceeding the normal maximum peak
current established by the current control stages within the
IC. To prevent these spurious spikes from conveying errone-
ous information to the Current Comparator, a 100ns blanking
signal is applied to the current monitoring circuitry. Thus,
there is no peak current protection during the first 6% of the
duty cycle (see Figure 36).
DUTY CYCLE
1.0
0.06
1
3
5
7
P
0.375
DMOS Transistor Turn-On Noise
Although the large DMOS transistor turn-on current spikes are
“blanked over” by the control circuit, it is important to minimize
these current spikes, since they often result in voltage spikes
considerably below the device substrate that can activate par-
asitic devices within the IC. Such activation of parasitic
devices will often result in improper operation of the IC. An
external terminal labeled V
G
brings out the power supply to
the gate drive circuitry. This allows for the control of the peak
current delivered to the gate of the DMOS transistor, which in
turn establishes the turn-on speed. The V
G
pin may be exter-
nally bypassed for the fastest possible turn-on, or series resis-
tance may be added with no bypassing capacitor to slow
down the turn-on of the DMOS transistor. Depending upon the
actual layout of the supply, it is generally recommended that a
series resistor be added (10
-150
) so that the DMOS tran-
sistor turn-on speed is reduced. By properly adjusting the
turn-on speed, undershoot can be avoided while turn-on
switching losses are kept to a minimum.
Soft Start Implementation
It is often desirable to allow the regulator to start up slowly,
Figure 35 shows one means of implementing this action. The
normally high output current from the HIP5061 transconduc-
tance amplifier (when V
FB
= 0 and V
REF
= 5.1V) is directed to
an external capacitor through a diode. This slows down the
rate of rise of the voltage at the V
C
terminal. After the regula-
tor starts, the external capacitor is charged to V
DD
and is
effectively removed from the frequency compensation net-
work by a reverse biased diode. To ensure rapid recycling of
the capacitor voltage with removal of power, a diode is placed
across the 100k
resistor. Logic Shutdown Input (V
C
Pin).
FIGURE 35. SOFT START CIRCUIT FOR THE HIP5061
The DC to DC converter may be shut down by returning the
V
C
output terminal to ground. A sinking current greater than
4mA will insure that this output is pulled to ground. It must be
remembered that once switching operation ceases, the drain
of the DMOS transistor is open. When the supply is in the
Boost configuration, the output voltage is not zero but the input
voltage less diode and inductor voltage drops. If the SEPIC
0.1
μ
F
20
μ
F
HIP5061
GATE DRIVER
AND CONTROL
CIRCUITRY
V
DD
V
G
DRAIN
FB
V
C
GND
SOURCE
SOFT START
NETWORK
TYPICAL FREQUENCY
COMPENSATION NETWORK
2mA, TYP
100k
100k
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