參數(shù)資料
型號(hào)： HIP5061DS
廠商： INTERSIL CORP
元件分類(lèi)： 穩(wěn)壓器
英文描述： FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
中文描述： 12 A SWITCHING REGULATOR, 290 kHz SWITCHING FREQ-MAX, PZFM7
封裝： STAGGERED GULL WING, TO-220, SIP-7
文件頁(yè)數(shù)： 12/20頁(yè)
文件大?。?/td> 158K
代理商： HIP5061DS
7-64
HIP5061
Typical Application Circuit
Figure 33 shows a Simplified Block Diagram of the HIP5061 in a
typical Boost converter. A resistor connected from the V
IN
supply
to the V
DD
terminal of the IC powers the internal 14V shunt
regulator. The Gate Driver supply is decoupled from the main
supply by a small external resistor connected between V
DD
and
the V
G
terminal. A bypass capacitor is connected between the
V
DD
terminal and ground to reduce coupling between analog and
digital circuitry. A Schottky diode insures efficient energy transfer
from the DMOS drain circuit inductor to the load. To set the
output voltage, two resistors are used to scale the output supply
voltage down to the 5.1V internal reference.
The heart of the IC is the high current DMOS power
transistor with its associated gate driver and high-speed
peak current control loop. A portion of the converters DC
output is applied to a transconductance error amplifier that
compares the fed back signal with the internal 5.1V
reference. The output of this amplifier is brought out at
the V
C
terminal to provide for soft start and frequency
compensation of the control loop. This same signal is also
applied internally to program the peak DMOS transistor
drain current. To assure precise current control, the
response time of this peak current control loop is less
than 50ns.
A 2MHz internal clock provides all the timing signals for the
converter operating at 250kHz. A slope compensation circuit
is also incorporated within the converter IC to eliminate sub-
harmonic oscillation that occurs in continuous-current mode
converters operating with duty cycles greater than 50%.
HIP5061 Description of Operation
Figure 2 shows a more detailed Functional Block Diagram of
the HIP5061. An internal 14V shunt regulator in conjunction
with an external series resistor provides internal operating
voltage to the IC in applications where no 12V auxiliary sup-
ply is available. Note that In applications where the input
voltage at V
DD
is 12V, +/-10%, the regulator is not used. This
regulator is shown as a zener diode on the diagrams of Fig-
ure 2 and Figure 33.
The 2MHz clock is processed in the Control Logic block to
provide various timing signals. A cycle of operation begins
when a 100ns pulse (which occurs at a 4
μ
s interval) triggers
the latch that initiates the DMOS transistor on-time. This
pulse also provides a blanking interval in the Current Moni-
toring block to eliminate false turn-offs caused by high tran-
sient pulse currents that occur during turn-on. The output of
FIGURE 33. SIMPLIFIED BLOCK DIAGRAM OF THE HIP5061 IN A TYPICAL "BOOST" CONFIGURATION
SLOPE
COMPENSATION
5.1V
REFERENCE
GATE
DRIVER
CONTROL
LOGIC
V
DD
CLAMP
V
DD
HIP5061
2MHz
CLOCK
OVER
TEMP
UNDER
VOLTAGE
V/I
AMP
V
C
FB
GND
DRAIN
V
G
(SOURCE)
V
OUT
V
IN
2.6V
TAB
相關(guān)PDF資料
PDF描述
HIP5062 FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
HIP5062DW FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
HIP5062DY FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
HIP5063 FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
HIP5063DW FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HIP5061DS WAF 制造商:Harris Corporation 功能描述:
HIP5062 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Power Control IC Single Chip Dual Switching Power Supply
HIP5062DW 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Power Control IC Single Chip Dual Switching Power Supply
HIP5062DY 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Power Control IC Single Chip Dual Switching Power Supply
HIP5063 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Power Control IC Single Chip Power Supply
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