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參數(shù)資料
| 型號(hào)： | HFA3861BIN96 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, PLASTIC, MS-026ACD, TQFP-64 |
| 文件頁數(shù)： | 28/36頁 |
| 文件大小： | 733K |
| 代理商： | HFA3861BIN96 |
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CONFIGURATION REGISTER 31 ADDRESS (3Eh) MANUAL TX POWER CONTROL
Bits 7:1
7 bits to DAC input, -64 to 63 range
Bit 0
unused
CONFIGURATION REGISTER 32 ADDRESS (40h) R/W TEST MODES 1
Bit 7
Selection bit for DAC input test mode 7
0 = Barker
1 = Low rate I/Q samples
Bit 6
force high rate mode
0 = normal
1 = force high rate mode
Bit 5
Length Field counter
0 = disable (non 802.11 systems, length field may be in bits not microseconds)
1 = enabled
Bit 4
Tristate test bus and enable inputs
0 = Normal
1 = enable inputs on test bus
Bit 3
Disable spread sequence for 1 and 2Mbps
0 = Normal
1 = disabled
Bit 2
Disable scrambler
0 = normal scrambler operation
1 = scrambler disabled (taps set to 0)
Bit 1
PN generator enable (RX 44MHz clock)
0 = not enabled
1 = enabled. Bit must first be written to a ‘0’ before a ‘1’ to initialize logic.
Bit 0
PN generator enable (RX 22MHz clock)
0 = not enabled
1 = enabled. Bit must first be written to a ‘0’ before a ‘1’ to initialize logic.
CONFIGURATION REGISTER ADDRESS 33 (42h) R/W TEST MODES 2
Bit 7
Unused, set to 0
Bit 6
Disable locked timing capability.
0 = enable detection of Service field bit showing that the carrier and bit timing are locked to the same oscillator.
1 = disable detection and assume no lock.
Note. for locked timing operation, bit 2 of the received Service field as well as bit 2 of CR6 of the receiver must be a “1”.
Bit 5
DC offset compensation control
0 = enable DC offset compensation
1 = disable DC offset compensation
Bit 4
Bypass I/Q A/Ds.
0 = disable bypass
1 = 4 MSBs of I/Q data are input on test bus. TESTin 3:0 is [5:2], TESTin 7:4 is Q[5:2], LSBs are zeroed.
Bit 3
disable time adjust during packet. Note: this turns off bit tracking.
0 = normal
1 = disabled
Bit 2
Internal digital loop back mode (SDI pin becomes LOCK input to acquisition block)
0 = normal chip operation loop back disabled
1 = loop back enabled, A/D and D/A converters bypassed, chip will not respond to external signals
Bit 1
enable PN to lower test bus address (2-0)
0 = normal
1 = PN to test bus address
Bit 0
enable PN to upper test bus address (7-3)
0 = normal
1 = PN to test bus address
HFA3861B
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HFA3861IV | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861IV96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863IN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863IN96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
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