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參數資料
| 型號： | HFA3861BIN96 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, PLASTIC, MS-026ACD, TQFP-64 |
| 文件頁數： | 26/36頁 |
| 文件大?。?/td> | 733K |
| 代理商： | HFA3861BIN96 |
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CONFIGURATION REGISTER 15 ADDRESS (1Eh) R/W AGC GAIN CLIP
Bit 7
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bits 6:0
AGC gain clip (7-bit value, 0-127) this is the attenuator accumulator upper limit. The lower limit is 0.
CONFIGURATION REGISTER 16 ADDRESS (20h) R/W AGC SAT COUNTS
Bits 7:4
AGC mid Sat counts (0-15 range) these are the counts to kick in the attenuator steps (CR28).
Bits 3:0
AGC low Sat Count (0-15 range)
CONFIGURATION REGISTER 17 ADDRESS (22h) R/W AGC UPDATE CONTROL
Bit 7
AGC update during CIR injest.
0 = stop AGC updates during CIR buffer injest.
1 = enable AGC updates during CIR buffer injest.
Bit 6
Unused, set to 0
Bit 5:0
AGC timer count (number of clocks in AGC cycle, 32-63 range). Note: Timer count must be > 31.
CONFIGURATION REGISTER 18 ADDRESS (24h) R/W AGC HI SAT
Bits 7:4
AGC high sat attenuation (0-30). Note: hi sat attenuation step is actual value programmed times 2. This attenuation step will
occur if the # of I and Q saturations is greater than hi sat count.
Note: hi sat attenuation step actual value is programmed value times 2. This attenuation step will occur if the # of I and Q sats
is greater than hi sat count.
Bits 3:0
AGC hi sat count (0-15 range)
CONFIGURATION REGISTER 19 ADDRESS (26h) R/W AGC LOCK IN LEVEL
Bits 7:5
CW detector scale multiplication factor. (xxxx.x). See CR35 and CR 49. Set to 00h for forcing CW detect always active.
Bits 4:0
AGC Lock-in level (0-7.5 range). Note inner lock window.
CONFIGURATION REGISTER 20 ADDRESS (28h) R/W AGC LOCK WINDOW POS.
Bits 7:5
R/W, But Not Used Internally
Bit 4:0
AGC Lock Window positive side (0-15.5 range). Note: outer lock window.
CONFIGURATION REGISTER 21 ADDRESS (2Ah) R/W AGC BACKOFF
Bits 7,6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bits 5:0
AGC Backoff (xxxxx.x, 0-31.5 range) in half dB steps. This sets the operating headroom in the I and Q ADCs.
CONFIGURATION REGISTER 22 ADDRESS (2Ch) R/W AGC LOOKUP TABLE ADDRESS
Bits 7,6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bits 5
AGC Look up table read control bit
1 = Read AGC table at address given below
0 = Read contents of CR23
Bits 4:0
AGC lookup table address (32 address bits)
CONFIGURATION REGISTER 23 ADDRESS (2Eh) R/W AGC TABLE DATA
Bits 7
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bits 6:0
AGC look up table data unsigned
CONFIGURATION REGISTER 24 ADDRESS (30h) R/W AGC LOOP GAIN
Bits 7
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 6:0
AGC loop gain (0.xxxx - x.00000, 0 - 1.0000 range), nominally 0.7
HFA3861B
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HFA3861IV | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861IV96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863IN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863IN96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
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