參數(shù)資料
型號: HFA3861BIN96
廠商: INTERSIL CORP
元件分類: 無繩電話/電話
英文描述: Direct Sequence Spread Spectrum Baseband Processor
中文描述: TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP64
封裝: 10 X 10 MM, PLASTIC, MS-026ACD, TQFP-64
文件頁數(shù): 24/36頁
文件大?。?/td> 733K
代理商: HFA3861BIN96
24
Bits 5:4
SFD Time-out values
00 = 56
μ
s
01 = 64
μ
s
10 = 128
μ
s
11 = 144
μ
s
Bit 3
MD_RDY control
0 = After CRC16
1 = After SFD
Bit 2
Force Frequency Offset Estimating in all antenna diversity timelines.
0 = disabled
1 = enabled
Bit 1
Antenna choice for Receiver when single antenna acquisition is selected
0 = Antenna select pin low
1 = Antenna select pin high
Bit 0
Single or dual antenna acquire
0 = dual antenna for diversity acquisition
1 = single antenna
CONFIGURATION REGISTER 10 ADDRESS (14h) R/W RX CONFIGURE (Continued)
CONFIGURATION REGISTER 11 ADDRESS (16h) R/W RX-TX CONFIGURE
Bit 7
Continuous internal RX 22 and 44MHz clocks; (Only Reset active will stop) overrides CR10 bit 6.
This bit should be first loaded to a “1” then to a “0” during initial register loading to insure receiver initialization.
Bit 6
A/D input coupling
0 = DC
1 = AC (external bias network required)
Bit 5
TX filter / CMF weight select
0 = US
1 = Japan
Bit 4
Ping Pong Differential Encode enable
0 = disabled Ping Pong Differential encoding
1 = normal Ping Pong Differential encoding
Bit 3
CCA mode
0 = normal CCA. CCA will immediately respond to changes in ED, CS1, and SQ1 as configured
1 = Sampled CCA. CCA will update once per slot (20
μ
s), will be valid at 19.8
μ
s or 15.8
μ
s as determined by CR9 bit 7.
Bits 2:0
Precursor value in CIR estimate
CONFIGURATION REGISTER 12 ADDRESS (18h) R/W A/D TEST MODES 1
Bit 7
All DAC and A/D clock source control
0 = normal internal clocks
1 = clock via SDI pin
Bit 6
TX DAC clock
0 = enable
1 = disable
Bit 5
RX DAC clock
0 = enable
1 = disable
Bit 4
I DAC clock
0 = enable
1 = disable
Bit 3
Q DAC clock
0 = enable
1 = disable
Bit 2
RF A/D clock
0 = enable
1 = disable
HFA3861B
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