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參數(shù)資料
| 型號(hào)： | HFA3861A |
| 廠商： | Intersil Corporation |
| 元件分類： | 基帶處理器 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor(直接序列擴(kuò)頻基帶處理器) |
| 中文描述： | 直接序列擴(kuò)頻基帶處理器（直接序列擴(kuò)頻基帶處理器） |
| 文件頁數(shù)： | 28/36頁 |
| 文件大小： | 279K |
| 代理商： | HFA3861A |
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CONFIGURATION REGISTER 32 ADDRESS (40h) R/W TEST MODES 1
Bit 7
Selection bit for DAC input test mode 7
0 = Barker
1 = Low rate I/Q samples
Bit 6
force high rate mode
0 = normal
1 = force high rate mode
Bit 5
TX 44 clock enable
0 = Normal
1 = enabled
Bit 4
Tristate test bus and enable inputs
0 = Normal
1 = enable inputs on test bus
Bit 3
Disable spread sequence for 1 and 2Mbps
0 = Normal
1 = disabled
Bit 2
Disable scrambler
0 = normal scrambler operation
1 = scrambler disabled (taps set to 0)
Bit 1
PN generator enable (RX 44MHz clock)
0 = not enabled
1 = enabled. Bit must first be written to a ‘0’ before a ‘1’ to initialize logic.
Bit 0
PN generator enable (RX 22MHz clock)
0 = not enabled
1 = enabled. Bit must first be written to a ‘0’ before a ‘1’ to initialize logic.
CONFIGURATION REGISTER ADDRESS 33 (42h) R/W TEST MODES 2
Bits 7:6
Unused, set to 0
Bit 5
DC offset control
0 = enable DC offset compensation
1 = disable DC offset compensation
Bit 4
Bypass I/Q A/Ds.
0 = disable bypass
1 = 4 MSBs of I/Q data are input on test bus. TESTin 3:0 is [5:2], TESTin 7:4 is Q[5:2], LSBs are zeroed.
Bit 3
disable time adjust
0 = normal
1 = disabled
Bit 2
Internal digital loop back mode (SDI pin becomes LOCK input to acquisition block)
0 = normal chip operation loop back disabled
1 = loop back enabled, A/D and D/A converters bypassed, chip will not respond to external signals
Bit 1
enable PN to lower test bus address (2-0)
0 = normal
1 = PN to test bus address
Bit 0
enable PN to upper test bus address (7-3)
0 = normal
1 = PN to test bus address
CONFIGURATION REGISTER ADDRESS 34 (44h) R/W TEST BUS ADDRESS
Bits 7:0
address bits for various tests. See Tech Brief #TBD for a description of the factory test modes
CONFIGURATION REGISTER ADDRESS 35 (46h) R/W CMF COEFFICIENT CONTROL THRESHOLD
Bit 7
Threshold control
0 = threshold is relative to noise floor
1 = threshold is absolute.
Bit 6:0
Threshold. For 100% calculated weights, set to 80h and set CR19[7:4] to 02h. For 100% default weights, set to 7fh and set
CR19[7:4] to 00h.
HFA3861A
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| HFA3861B | Direct Sequence Spread Spectrum Baseband Processor(直接序列擴(kuò)譜基帶處理器) |
| HFA3861 | Direct Sequence Spread Spectrum (DSSS) baseband processor(直接序列擴(kuò)頻基帶處理器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HFA3861AIN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processo |
| HFA3861AIN96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processo |
| HFA3861B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861BIN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861BIN96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
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