參數(shù)資料
型號(hào)： HFA3861A
廠商： Intersil Corporation
元件分類： 基帶處理器
英文描述： Direct Sequence Spread Spectrum Baseband Processor(直接序列擴(kuò)頻基帶處理器)
中文描述： 直接序列擴(kuò)頻基帶處理器（直接序列擴(kuò)頻基帶處理器）
文件頁(yè)數(shù)： 14/36頁(yè)
文件大小： 279K
代理商： HFA3861A
14
In the 1Mbps DBPSK mode, data demodulation is performed
the same as in header processing. In the 2Mbps DQPSK
mode, the demodulator demodulates two bits per symbol
and differentially decodes these bit pairs. The bits are then
serialized and descrambled prior to being sent to the output.
In the CCK modes, the receiver removes carrier frequency
offsets and uses a bank of correlators to detect the
modulation. A biggest picker finds the largest correlation in
the I and Q Channels and determines the sign of those
correlations. For this to happen, the demodulator must know
the starting phase which is determined by referencing the
data to the last bit of the header. Each symbol demodulated
determines 1 or 2 nibbles of data. This is then serialized and
descrambled before being passed to the output.
Chip tracking in the CCK modes is chip decision directed.
Carrier tracking is via a lead/lag filter using a digital Costas
phase detector.
Acquisition Description
A projected worst case time line for the acquisition of a
signal with a short preamble and header is shown. The
synchronization part of the preamble is 56 symbols long
followed by a 16-bit SFD. The receiver must monitor the
antenna to determine if a signal is present. The timeline is
broken into 10
μ
s blocks (dwells) for the scanning process.
This length of time is necessary to allow enough integration
of the signal to make a good acquisition decision. This worst
case time line example assumes that the signal arrives part
way into the first dwell such as to just barely catch detection.
The signal and the scanning process are asynchronous and
the signal could start anywhere. In this timeline, it is
assumed that the signal is present in the first 10
μ
s dwell, but
was missed due to power amplifier ramp up.
Meanwhile signal quality and signal frequency
measurements are made simultaneous with symbol timing
measurements. A CS1 followed by SQ1 active, or two
consecutive SQ1’s will cause the part to exit the acquisition
phase and enter the tracking phase.
Prior to initial acquisition the NCO was inactive and DPSK
demodulation processing was used. Carrier phase
measurement are done on a symbol by symbol basis
afterward and coherent DPSK demodulation is in effect.
After a brief setup time as illustrated on the timeline of, the
signal begins to emerge from the demodulator.
It takes 7 more symbols to seed the descrambler before
valid data is available. This occurs in time for the SFD to be
received. At this time the demodulator is tracking and in the
coherent PSK demodulation mode it will no longer
acquire signals.
2
20 SYMBOLS
56 SYMBOL SYNC
SFD
TX
POWER
RAMP
20 SYMBOLS
7 SYM
16 SYMBOLS
AGC SETTLE AND LOCK
AND INITIAL DETECTION
VERIFY AND CIR/FREQUENCY
ESTIMATION AND CMF/NCO
JAMMING
SFD DET
START DATA
SEED
DESCRAMBLER
START SFD DETECTION
FIGURE 10. ACQUISITION TIMELINE
HFA3861A
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HFA3861AIN 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processo
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HFA3861BIN 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor
HFA3861BIN96 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor
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