參數(shù)資料
型號(hào)： HFA3861A
廠商： Intersil Corporation
元件分類： 基帶處理器
英文描述： Direct Sequence Spread Spectrum Baseband Processor(直接序列擴(kuò)頻基帶處理器)
中文描述： 直接序列擴(kuò)頻基帶處理器（直接序列擴(kuò)頻基帶處理器）
文件頁(yè)數(shù)： 26/36頁(yè)
文件大?。?/td> 279K
代理商： HFA3861A
26
CONFIGURATION REGISTER 16 ADDRESS (20h) R/W AGC CONTROL 2
Bits 7:4
AGC mid Sat counts (0-15 range) these are the counts to kick in the attenuator steps (CR28).
Bits 3:0
AGC low Sat Count (0-15 range)
CONFIGURATION REGISTER 17 ADDRESS (22h) R/W AGC CONTROL 4
Bits 7:6
Unused, set to 0
Bit 5:0
AGC timer count (number of clocks in AGC cycle, 32-63 range). Note: Timer count must be > 31.
CONFIGURATION REGISTER 18 ADDRESS (24h) R/W AGC CONTROL 5
Bits 7:4
AGC high sat attenuation (0-30). Note: hi sat attenuation step is actual value programmed times 2. This attenuation step will
occur if the # of I and Q saturations is greater than hi sat count.
Bits 3:0
AGC hi sat count (0-15 range)
CONFIGURATION REGISTER 19 ADDRESS (26h) R/W AGC CONTROL 6
Bits 7:5
CW detector scale multiplication factor. (xxxx.x). See CR35 for forcing default weights.
Bits 4:0
AGC Lock-in level (0-7.5 range)
CONFIGURATION REGISTER 20 ADDRESS (28h) R/W AGC CONTROL 7
Bits 7:5
R/W, But Not Used Internally
Bit 4:0
AGC Lock Window positive side (0-15.5 range). Note: outer lock window.
CONFIGURATION REGISTER 21 ADDRESS (2Ah) R/W AGC CONTROL 8
Bits 7,6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bits 5:0
AGC Backoff (xxxxx.x, 0-31.5 range)
CONFIGURATION REGISTER 22 ADDRESS (2Ch) R/W AGC CONTROL 9
Bits 7,6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bits 5
AGC Look up table read control bit
1 = Read AGC table at address given below
0 = Read contents of CR23
Bits 4:0
AGC lookup table address (32 address bits)
CONFIGURATION REGISTER 23 ADDRESS (2Eh) R/W AGC CONTROL 10
Bits 7
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bits 6:0
AGC look up table data unsigned
CONFIGURATION REGISTER 24 ADDRESS (30h) R/W AGC CONTROL 11
Bits 7
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 6:0
AGC loop gain (0.xxxx - x.00000, 0 - 1.0000 range)
CONFIGURATION REGISTER 25 ADDRESS (32h) R/W AGC CONTROL 12
Bits 7
AGC RX_RF, This input drives the RX-RF control if AGC override Enable is set to 1
Bits 6:0
AGC RX_IF, This reg is input to RF-IF DAC if AGC override Enable is set to 1. When polarity bit is zero, a “1” removes 30dB
pad, a “0” inserts 30dB pad.
HFA3861A
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HFA3861AIN 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processo
HFA3861AIN96 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processo
HFA3861B 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor
HFA3861BIN 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor
HFA3861BIN96 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor
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