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參數(shù)資料
| 型號(hào)： | HDMP-1526 |
| 英文描述： | Transistor Diode Kit;Contents Of Kit:Transistor/Diode Kit |
| 中文描述： | 光纖通道收發(fā)器芯片 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 229K |
| 代理商： | HDMP-1526 |
686
HDMP-1526 (Receiver Section)
Timing Characteristics
T
C
= 0
°
C to +85
°
C, V
CC
= 4.5 V to 5.25 V
Symbol
b_sync
[1,2]
f_lock
[2]
Parameter
Units
bits
μ
sec
Min.
Typ.
Max.
2500
500
Bit Sync Time
Frequency Lock Time
(from Time of Setting -LCKREF = 0)
Frequency Lock Rate (when -LCKREF = 0)
Time Data Valid Before Rising Edge of RBC
Time Data Valid After Rising Edge of RBC
RBC Duty Cycle
Rising Edge Time Difference
Receiver Latency
f_lock_rate
[2]
t
valid_before
t
valid_after
t
duty
t
A-B[3]
t_rxlat
[4]
kHz/
μ
sec
nsec
nsec
%
nsec
nsec
bits
200
5.8
3.3
3
1.5
40
8.9
60
9.9
33.9
36
9.4
25.0
26.6
Notes:
1. This is the recovery time for input phase jumps, per the FC-PH specification Ref 4.1, Sec 5.3.
2. Tested using C
PLL
= 0.01
μ
F.
3. The RBC clock skew is calculated as t
A-B(max)
- t
A-B(min)
.
4. The receiver latency, as shown in Figure 5, is defined as the time between receiving the first serial bit of a parallel data word (as
defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive
byte clock, either RBC1 or RBC0).
DATA
DATA
RX[0]-RX[9]
t-VALID BEFORE
t-VALID AFTER
RBC1
K28.5
DATA
DATA
1.4 V
2.0 V
0.8 V
2.0 V
BYTSYNC
RBC0
0.8 V
1.4 V
Figure 6. Receiver Latency.
DATA BYTE A
DATA BYTE D
RX[0]-RX[9]
DATA BYTE D
± DIN
1.4 V
t_RXLAT
R5
R6
R7
R8
R9
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R2
R3
R4
R5
RBC1/0
DATA BYTE C
Figure 5. Receiver Section.
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