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參數(shù)資料
| 型號： | HDMP-1526 |
| 英文描述： | Transistor Diode Kit;Contents Of Kit:Transistor/Diode Kit |
| 中文描述： | 光纖通道收發(fā)器芯片 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 229K |
| 代理商： | HDMP-1526 |
685
HDMP-1526 (Transmitter Section)
Timing Characteristics
T
C
= 0
°
C to +85
°
C, V
CC
= 4.5 V to 5.25 V
Symbol
t
setup
t
hold
t_txlat
[1]
Parameter
Setup Time
Hold Time
Transmitter Latency
Units
nsec
nsec
nsec
bits
Min.
2
1.5
Typ.
Max.
6.25
6.64
12.2
13.0
Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered
by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by the
rising edge of the first bit transmitted).
Figure 3. Transmitter Section Timing.
DATA
DATA
TX[0]-TX[9]
t-SETUP
t-HOLD
REFCLK
DATA
DATA
DATA
1.4 V
2.0 V
0.8 V
Figure 4. Transmitter Latency.
DATA BYTE B
DATA BYTE C
TX[0]-TX[9]
DATA BYTE A
± DOUT
1.4 V
DATA BYTE B
t_TXLAT
T5
T6
T7
T8
T9
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T0
T1
T2
T3
T4
T5
REFCLK
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